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ADV7390BCPZ 데이터시트(PDF) 11 Page - Analog Devices |
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ADV7390BCPZ 데이터시트(HTML) 11 Page - Analog Devices |
11 / 96 page ADV7390/ADV7391/ADV7392/ADV7393 Rev. 0 | Page 11 of 96 CONTROL OUTPUTS PIXEL PORT *LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2. Y1 Cr0 Y0 Cb0 XY 00 00 3FF CLKIN* t9 t10 t12 t11 t12 t11 t14 t13 Figure 7. ED/HD-DDR Input, 8-/10-Bit 4:2:2 YCrCb (EAV/SAV), Input Mode 010 CLKIN CONTROL OUTPUTS Y1 Cr0 Y0 Cb0 Cr2 Y2 Cb2 t9 t10 t12 t11 t13 t14 PIXEL PORT HSYNC VSYNC CONTROL INPUTS Figure 8. ED (at 54 MHz) Input, 8-/10-Bit 4:2:2 YCrCb (HSYNC/VSYNC), Input Mode 111 CLKIN CONTROL OUTPUTS 3FF 00 00 XY Cb0 Y0 Cr0 Y1 PIXEL PORT t11 t12 t10 t9 t14 t13 Figure 9. ED (at 54 MHz) Input, 8-/10-Bit 4:2:2 YCrCb (EAV/SAV), Input Mode 111 |
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