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S71NS-J ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 3 Page - SPANSION

๋ถ€ํ’ˆ๋ช… S71NS-J
์ƒ์„ธ๋‚ด์šฉ  Stacked Multi-Chip Product (MCP)
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์ œ์กฐ์‚ฌ  SPANSION [SPANSION]
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This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design
in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
Publication Number S71NS-J_00
Revision 03
Issue Date October 10, 2006
Features
Single 1.8 volt read, program and erase (1.7 to 1.95 V)
Multiplexed Data and Address for reduced
I/O count
โ€“ A15โ€“A0 multiplexed as DQ15โ€“DQ0
โ€“ Addresses are latched by AVD# control input when CE# low
Simultaneous Read/Write operation
โ€“ Data can be continuously read from one bank while executing
erase/program functions in other bank
โ€“ Zero latency between read and write operations
Package
โ€“ 56-ball Very Thin FBGA
Product Selector Guide
General Description
The products covered by this document are listed in the table below
S71NS-J
Stacked Multi-Chip Product (MCP)
110 nm CMOS 1.8 Volt-only Simultaneous Read/Write,
Burst Mode Multiplexed Flash Memory with pSRAM
Data Sheet (Advance Information)
MCP
Flash
pSRAM
pSRAM Type
pSRAM Read
OPN
S71NS032JA0
S29NS032J
16 Mb
Mux pSRAM 2
Asynchronous only
S71NS032JA0BJWRT
S71NS032J80
S29NS032J
8 Mb
Mux pSRAM 1
Asynchronous only
S71NS032J80BJWRA
Document
Publication Identification Number
S29NS-J
S29NS-J_00
8 Mb Multiplexed pSRAM Type 1
muxpsram_06
16Mb Multiplexed pSRAM Type 2 (Asynchronous only)
muxpsram_05


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