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S71NS-J ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 7 Page - SPANSION

๋ถ€ํ’ˆ๋ช… S71NS-J
์ƒ์„ธ๋‚ด์šฉ  Stacked Multi-Chip Product (MCP)
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S71NS-J ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 7 Page - SPANSION

   
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S71NS-J_00_03 October 10, 2006
S71NS-J
5
Data
Sheet
(Ad v anc e
I nf o r mation)
4.
Ordering Information
The order number (Valid Combination) is formed by the following:
S71NS
032
J
A0
BJ
W
RT
0
PACKING TYPE
0 = Tray
2 = 7-inch Tape and Reel
3 = 13-inch Tape and Reel
ADDITIONAL ORDERING OPTIONS
See Valid Combinations Table
TEMPERATURE RANGE
W = Wireless (โ€“25
ยฐC to +85ยฐC)
For Industrial (โ€“40
ยฐC to +85ยฐC), contact local sales office
PACKAGE TYPE
BJ = Very Thin Fine-Pitch BGA Lead (Pb)-Free LF35 Package
pSRAM DENSITY
A0 = 16 Megabit (1M x 16-Bit)
FLASH PROCESS TECHNOLOGY
J = 110 nm Floating Gate Technology
FLASH DENSITY
064 = 64 Megabit (4 M x 16-Bit)
032 = 32 Megabit (2M x 16-Bit)
DEVICE FAMILY
S71NS = Stacked Multi-Chip Product,
Simultaneous Read/Write, Burst Mode Flash Memory with Multiplexed I/O
1.8-Volt Operation, Top Boot Sectors, and pSRAM
Table 4.1 Valid Combinations
Base OPN
Density
Process
Technology
pSRAM
Density
Package Type
Temperature
Options
Packing Type
S71NS
032
J
80
BJ
W
RA
0, 2, 3
A0
RT


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