전자부품 데이터시트 검색엔진 |
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S71NS-J 데이터시트(PDF) 7 Page - SPANSION |
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S71NS-J 데이터시트(HTML) 7 Page - SPANSION |
7 / 9 page S71NS-J_00_03 October 10, 2006 S71NS-J 5 Data Sheet (Ad v anc e I nf o r mation) 4. Ordering Information The order number (Valid Combination) is formed by the following: S71NS 032 J A0 BJ W RT 0 PACKING TYPE 0 = Tray 2 = 7-inch Tape and Reel 3 = 13-inch Tape and Reel ADDITIONAL ORDERING OPTIONS See Valid Combinations Table TEMPERATURE RANGE W = Wireless (–25 °C to +85°C) For Industrial (–40 °C to +85°C), contact local sales office PACKAGE TYPE BJ = Very Thin Fine-Pitch BGA Lead (Pb)-Free LF35 Package pSRAM DENSITY A0 = 16 Megabit (1M x 16-Bit) FLASH PROCESS TECHNOLOGY J = 110 nm Floating Gate Technology FLASH DENSITY 064 = 64 Megabit (4 M x 16-Bit) 032 = 32 Megabit (2M x 16-Bit) DEVICE FAMILY S71NS = Stacked Multi-Chip Product, Simultaneous Read/Write, Burst Mode Flash Memory with Multiplexed I/O 1.8-Volt Operation, Top Boot Sectors, and pSRAM Table 4.1 Valid Combinations Base OPN Density Process Technology pSRAM Density Package Type Temperature Options Packing Type S71NS 032 J 80 BJ W RA 0, 2, 3 A0 RT |
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