전자부품 데이터시트 검색엔진
  Korean  ▼

Delete All
ON OFF
ALLDATASHEET.CO.KR

X  

Preview PDF Download HTML

S71WS512NE0BFWZZ 데이터시트(HTML) 4 Page - SPANSION

부품명 S71WS512NE0BFWZZ
상세내용  Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
Download  142 Pages
Scroll/Zoom Zoom In 100% Zoom Out
제조사  SPANSION [SPANSION]
홈페이지  http://www.spansion.com
Logo 

S71WS512NE0BFWZZ 데이터시트(HTML) 4 Page - SPANSION

 
Zoom Inzoom in Zoom Outzoom out
/ 142 page
 4 / 142 page
background image
4
S71WS512NE0BFWZZ_00_A1 June 28, 2004
Advan ce
In form ati o n
Chip Erase Command Sequence ................................................................... 58
Sector Erase Command Sequence .................................................................59
Erase Suspend/Erase Resume Commands .................................................. 60
Figure 4. Erase Operation.................................................... 61
Program Suspend/Program Resume Commands ...................................... 61
Lock Register Command Set Definitions ................................................... 62
Password Protection Command Set Definitions ..................................... 62
Non-Volatile Sector Protection Command Set Definitions ..................63
Global Volatile Sector Protection Freeze Command Set ..................... 64
Volatile Sector Protection Command Set ...................................................65
SecSi Sector Entry Command .........................................................................65
Command Definition Summary ..................................................................... 66
Write Operation Status . . . . . . . . . . . . . . . . . . . . .69
DQ7: Data# Polling ........................................................................................... 69
Figure 5. Data# Polling Algorithm......................................... 70
RDY: Ready .......................................................................................................... 70
DQ6: Toggle Bit I ............................................................................................... 70
Figure 6. Toggle Bit Algorithm.............................................. 71
DQ2: Toggle Bit II ...............................................................................................72
Table 19. DQ6 and DQ2 Indications ..................................... 72
Reading Toggle Bits DQ6/DQ2 ......................................................................72
DQ5: Exceeded Timing Limits ........................................................................73
DQ3: Sector Erase Timer .................................................................................73
DQ1: Write to Buffer Abort ............................................................................73
Table 20. Write Operation Status ......................................... 74
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . 75
Figure 7. Maximum Negative Overshoot Waveform................. 75
Figure 8. Maximum Positive Overshoot Waveform .................. 75
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 75
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .76
CMOS Compatible .............................................................................................76
Test Conditions ...................................................................................................77
Figure 9. Test Setup ........................................................... 77
Table 21. Test Specifications ............................................... 77
Switching Waveforms ........................................................................................77
Table 22. Key to Switching Waveforms ................................. 77
Figure 10. Input Waveforms and Measurement Levels............. 77
VCC Power-up ..................................................................................................... 78
Figure 11. VCC Power-up Diagram ........................................ 78
Pin Capacitance .................................................................................................. 78
AC Characteristics—Synchronous . . . . . . . . . . . 79
CLK Characterization ........................................................................................79
Figure 12. CLK Characterization ........................................... 79
Synchronous/Burst Read @ VIO = 1.8 V .....................................................80
Timing Diagrams .................................................................................................. 81
Figure 13. CLK Synchronous Burst Mode Read (rising active CLK).
....................................................................................... 81
Figure 14. Synchronous Burst Mode Read.............................. 82
Figure 15. Eight-word Linear Burst with Wrap Around ............. 82
Figure 16. Eight-word Linear Burst without Wrap Around......... 83
Figure 17. Linear Burst with RDY Set One Cycle Before Data.... 83
AC Characteristics—Asynchronous . . . . . . . . . . 84
Asynchronous Mode Read @ VIOpS = 1.8 V ............................................. 84
Timing Diagrams ................................................................................................. 84
Figure 18. Asynchronous Mode Read with Latched Addresses... 84
Figure 19. Asynchronous Mode Read..................................... 85
Hardware Reset (RESET#) .............................................................................. 85
Figure 20. Reset Timings..................................................... 85
Erase/Program Operations @ VIO = 1.8 V ................................................. 86
Figure 21. Asynchronous Program Operation Timings: WE#
Latched Addresses ............................................................. 87
Figure 22. Synchronous Program Operation Timings: CLK Latched
Addresses......................................................................... 88
Figure 23. Accelerated Unlock Bypass Programming Timing..... 88
Figure 24. Data# Polling Timings (During Embedded Algorithm) ...
........................................................................................ 89
Figure 25. Toggle Bit Timings (During Embedded Algorithm) ... 89
Figure 26. Synchronous Data Polling Timings/Toggle Bit Timings ..
........................................................................................ 90
Figure 27. DQ2 vs. DQ6 ..................................................... 90
Figure 28. Latency with Boundary Crossing when Frequency > 66
MHz................................................................................. 91
Figure 29. Latency with Boundary Crossing into Program/Erase
Bank................................................................................ 91
Figure 30. Example of Wait States Insertion.......................... 92
Figure 31. Back-to-Back Read/Write Cycle Timings ................ 92
Erase and Programming Performance . . . . . . . . 93
128Mb pSRAM
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
FUNCTION TRUTH TABLE . . . . . . . . . . . . . . . 95
Asynchronous Operation (Page Mode) ..................................................... 95
FUNCTION TRUTH TABLE (Continued) . . . . 96
Synchronous Operation (Burst Mode) .......................................................96
STATE DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . .97
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . 98
Power-up ...............................................................................................................98
Configuration Register ......................................................................................98
CR Set Sequence ................................................................................................98
FUNCTIONAL DESCRIPTION (Continued) . . 99
Address Key .........................................................................................................99
FUNCTIONAL DESCRIPTION (Continued) . 100
Power Down ...................................................................................................... 100
FUNCTIONAL DESCRIPTION (Continued) . . 101
Burst Read/Write Operation ..........................................................................101
FUNCTIONAL DESCRIPTION (Continued) . 102
CLK Input Function ..........................................................................................102
ADV# Input Function .......................................................................................102
WAIT# Output Function ................................................................................102
FUNCTIONAL DESCRIPTION (Continued) . . 103
Latency ..................................................................................................................103
FUNCTIONAL DESCRIPTION (Continued) . 104
Address Latch by ADV# .................................................................................104
Burst Length ........................................................................................................104
Single Write .........................................................................................................104
Write Control ....................................................................................................105
FUNCTIONAL DESCRIPTION (Continued) . 106
Burst Read Suspend ..........................................................................................106
Burst Write Suspend ........................................................................................106
FUNCTIONAL DESCRIPTION (Continued) . . 107
Burst Read Termination ..................................................................................107
Burst Write Termination ................................................................................107
ABSOLUTE MAXIMUM RATINGS (See
WARNING below.) . . . . . . . . . . . . . . . . . . . . . . 108
RECOMMENDED OPERATING CONDITIONS
(See WARNING below.) . . . . . . . . . . . . . . . . . . 108
(Referenced to VSS) ................................................................................... 108
DC CHARACTERISTICS
. . . . . (Under Recommended Operating Conditions
unless otherwise noted) . . . . . . . . Note *1,*2,*3 109


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62  63  64  65  66  67  68  69  70  71  72  73  74  75  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90  91  92  93  94  95  96  97  98  99  100   ...More


데이터시트 Download




링크 URL



Privacy Policy
ALLDATASHEET.CO.KR
ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ]  

Alldatasheet는?   |   광고문의    |   운영자에게 연락하기   |   개인정보취급방침   |   즐겨찾기   |   링크교환   |   제조사별 검색
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn