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S71WS512NE0BFWZZ 데이터시트(HTML) 49 Page - SPANSION

부품명 S71WS512NE0BFWZZ
상세내용  Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
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S71WS512NE0BFWZZ 데이터시트(HTML) 49 Page - SPANSION

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June 28, 2004 S71WS512NE0BFWZZ_00_A1
S29WSxxxN MirrorBit™ Flash Family For Multi-chip Products (MCP)
49
Ad vance
Info rmat i o n
Command Definitions
Writing specific address and data commands or sequences into the command
register initiates device operations. The "Command Definition Summary" section
defines the valid register command sequences. Writing incorrect address and
data values or writing them in the improper sequence may place the device in an
unknown state. The system must write the reset command to return the device
to reading array data. Refer to “AC Characteristics—Synchronous” and “AC Char-
acteristics—Asynchronous” for timing diagrams.
Reading Array Data
The device is automatically set to reading asynchronous array data after device
power-up. No commands are required to retrieve data in asynchronous mode.
Each bank is ready to read array data after completing an Embedded Program or
Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the corresponding bank
enters the erase-suspend-read mode, after which the system can read data from
any non-erase-suspended sector within the same bank. After completing a pro-
gramming operation in the Erase Suspend mode, the system may once again
read array data from any non-erase-suspended sector within the same bank. See
the "Erase Suspend/Erase Resume Commands" section for more information.
After the device accepts a Program Suspend command, the corresponding bank
enters the program-suspend-read mode, after which the system can read data
from any non-program-suspended sector within the same bank. See the "Pro-
gram Suspend/Program Resume Commands" section for more information.
The system must issue the reset command to return a bank to the read (or erase-
suspend-read) mode if DQ5 goes high during an active program or erase opera-
tion, or if the bank is in the autoselect mode. See the "Reset Command" section
for more information. If DQ1 goes high during Write Buffer Programming, the
system must issue the Write Buffer Abort Reset command.
See also "Requirements for Asynchronous Read Operation (Non-Burst)" section
and "Requirements for Synchronous (Burst) Read Operation" section for more in-
formation. The Asynchronous Read and Synchronous/Burst Read tables provide
the read parameters, and Figure 13, Figure 14, and Figure 18 show the timings.
Set Configuration Register Command Sequence
The device uses a configuration register to set the various burst parameters:
number of wait states, burst read mode, active clock edge, RDY configuration,
and synchronous mode active (see Figure 16 for details). The configuration reg-
ister must be set before the device will enter burst mode. On power up or reset,
the device is set in asynchronous read mode and the configuration register is re-
set. The configuration register is not reset after deasserting CE#.
The configuration register is loaded with a four-cycle command sequence. The
first two cycles are standard unlock sequences. On the third cycle, the data
should be D0h and address bits should be 555h. During the fourth cycle, the con-
figuration code should be entered onto the data bus with the address bus set to
address 000h. Once the data has been programmed into the configuration regis-
ter, a software reset command is required to set the device into the correct state.
The device will power up or after a hardware reset with the default setting, which
is in asynchronous mode. The register must be set before the device can enter


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