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S71WS512NE0BFWZZ 데이터시트(HTML) 53 Page - SPANSION

부품명 S71WS512NE0BFWZZ
상세내용  Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
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S71WS512NE0BFWZZ 데이터시트(HTML) 53 Page - SPANSION

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June 28, 2004 S71WS512NE0BFWZZ_00_A1
S29WSxxxN MirrorBit™ Flash Family For Multi-chip Products (MCP)
53
Ad vance
Info rmat i o n
case, the RDY pin will always indicate that the device is ready to handle a new
transaction when low.
Configuration Register
Table 16 shows the address bits that determine the configuration register settings
for various device functions.
Reset Command
Writing the reset command resets the banks to the read or erase-suspend-read
mode. Address bits are don’t cares for this command.
The reset command may be written between the sequence cycles in an erase
command sequence before erasing begins. This resets the bank to which the sys-
tem was writing to the read mode. Once erasure begins, however, the device
ignores reset commands until the operation is complete.
Table 16. Configuration Register
CR BIt
Function
Settings (Binary)
CR15
Set Device
Read Mode
0 = Synchronous Read (Burst Mode) Enabled
1 = Asynchronous Mode (default)
CR14
Boundary
Crossing
0 = No extra boundary crossing latency
1 = With extra boundary crossing latency (default)
CR13
Programmable
Wait State
000 = Data is valid on the 2nd active CLK edge after addresses are latched
001 = Data is valid on the 3rd active CLK edge after addresses are latched
010 = Data is valid on the 4th active CLK edge after addresses are latched
011 = Data is valid on the 5th active CLK edge after addresses are latched
100 = Data is valid on the 6th active CLK edge after addresses are latched
101 = Data is valid on the 7th active CLK edge after addresses are latched (default)
110 = Reserved
111 = Reserved
CR12
CR11
CR10
RDY Polarity
0 = RDY signal is active low
1 = RDY signal is active high (default)
CR9
Set Internal
Clock
Frequency
0 = Reserved for Future Use
1 = Internal clock switches at full frequency of the external clock (default)
CR8
RDY
0 = RDY active one clock cycle before data
1 = RDY active with data (default)
CR7
Burst
Sequence
0 = Reserved for Future Use
1 = Sequential Burst Order (default)
CR6
Clock
0 = Burst starts and data is output on the falling edge of CLK
1 = Burst starts and data is output on the rising edge of CLK (default)
CR3
Burst Wrap
Around
0 = No Wrap Around Burst
1 = Wrap Around Burst (default)
CR2
Burst Length
000 = Continuous (default)
010 = 8-Word Linear Burst
011 = 16-Word Linear Burst
100 = 32-Word Linear Burst
(All other bit settings are reserved)
CR1
CR0
Notes: Device will be in the default state upon power-up or hardware reset.


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