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S71WS512NE0BFWZZ ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 8 Page - SPANSION

๋ถ€ํ’ˆ๋ช… S71WS512NE0BFWZZ
์ƒ์„ธ๋‚ด์šฉ  Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
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S71WS512NE0BFWZZ_00_A1 June 28, 2004
Advan ce
In form ati o n
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages
(FBGA). The package and/or data integrity may be compromised if the package
body is exposed to temperatures above 150ยฐC for prolonged periods of time.
Pin Description
A22โ€“A0
=
23 Address Inputs (Common)
A23
=
1 Address Inputs (Flash)
DQ15โ€“DQ0
=
16 Data Inputs/Outputs (Common)
CE#f
=
Chip Enable (Flash)
CE#1pS
=
Chip Enable1 (pSRAM)
CE#2pS
=
Chip Enable2 (pSRAM)
OE#
=
Output Enable (Common)
WE#
=
Write Enable (Common)
RDY
=
Ready Output
CLK
=
Clock Input
AVD#
=
Address Valid Input
UB#
=
Upper Byte Control (SRAM)
LB#
=
Lower Byte Control (SRAM)
RESET#
=
Hardware Reset Pin, Active Low (Flash)
WP#
=
Hardware Write Protect (Flash)
ACC
=
Acceleration pin (Flash)
VCCf
=
Flash 1.8 volt-only single power supply (see Product
Selector Guide for speed options and voltage supply
tolerances)
VCCps
=
pSRAM Power Supply
VIOps
=
pSRAM Output buffer Power Supply
Vss
=
Device Ground (Common)
NC
=
Pin Not Connected Internally
RFU
=
Reserved for Future Use


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