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S71WS512NE0BFWZZ 데이터시트(HTML) 93 Page - SPANSION

부품명 S71WS512NE0BFWZZ
상세내용  Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
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S71WS512NE0BFWZZ 데이터시트(HTML) 93 Page - SPANSION

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June 28, 2004 S71WS512NE0BFWZZ_00_A1
S29WSxxxN MirrorBit™ Flash Family For Multi-chip Products (MCP)
93
Ad vance
Info rmat i o n
Erase and Programming Performance
Notes:
1. Typical program and erase times assume the following conditions: 25
°C, 1.8 V VCC, 10,000 cycles;
checkerboard data pattern.
2. Under worst case conditions of 90°C, VCC = 1.65 V, 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed.
Based upon single word programming, not page programming.
4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before
erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program
command. See the "Command Definition Summary" section for further information on command definitions.
6. Contact the local sales office for minimum cycling endurance values in specific applications and operating
conditions.
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Comments
Sector Erase Time
64 Kword
VCC
<0.4
2.5
s
Excludes 00h
programming prior to
erasure (Note 4)
16 Kword
VCC
<0.15
2
Chip Erase Time
VCC
<104 (WS256N)
<208 (WS256N)
s
ACC
<86.7(WS256N)
<173.4 (WS256N)
Effective Word Programming Time
utilizing Program Write Buffer
VCC
<9.4
<18.8
µs
ACC
<4
<8
Total 32-Word Buffer
Programming Time
VCC
<300
<600
µs
ACC
<64
<128
Chip Programming Time (Note 3)
VCC
<335.5 (WS256N)
<671 (WS256N)
s
Excludes system level
overhead (Note 5)
ACC
<145.9 (WS256N)
<292 (WS256N)
Erase Suspend/Erase Resume
<20
µs
Program Suspend/Program
Resume
<20
µs


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