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S71WS512NE0BFWZZ ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 100 Page - SPANSION

๋ถ€ํ’ˆ๋ช… S71WS512NE0BFWZZ
์ƒ์„ธ๋‚ด์šฉ  Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
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128Mb pSRAM
S71WS512NE0BFWZZ_00_A1 June 28, 2004
Pr e l i m i n a r y
FUNCTIONAL DESCRIPTION (Continued)
Power Down
The Power Down is low power idle state controlled by CE2. CE2 Low drives the
device in power down mode and mains low power idle state as long as CE2 is kept
low. CE2 High resume the device from power down mode.
This device has three power down modes, Sleep, 16M Partial, and 32M Partial.
The selection of power down mode is set through CR Set sequence. Each mode
has following data retention features.
The default state is Sleep and it is the lowest power consumption but all data will
be lost once CE2 is brought to Low for Power Down. It is not required to perform
CR Set sequence to set to Sleep mode after power-up in case of asynchronous
operation.
Mode
Data Retention Size
Retention Address
Sleep [default]
No
N/A
16M Partial
16M bit
000000h to 0FFFFFh
32M Partial
32M bit
000000h to 1FFFFFh


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