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S71WS512NE0BFWZZ 데이터시트(HTML) 17 Page - SPANSION

부품명 S71WS512NE0BFWZZ
상세내용  Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
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S71WS512NE0BFWZZ 데이터시트(HTML) 17 Page - SPANSION

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June 28, 2004 S71WS512NE0BFWZZ_00_A1
S29WSxxxN MirrorBit™ Flash Family For Multi-chip Products (MCP)
17
Ad vance
Info rmat i o n
wide range of microprocessors/microcontrollers for high performance read
operations.
The burst read mode feature gives system designers flexibility in the interface to
the device. The user can preset the burst length and then wrap or non-wrap
through the same memory space, or read the flash array in continuous mode.
The clock polarity feature provides system designers a choice of active clock
edges, either rising or falling. The active clock edge initiates burst accesses and
determines when data will be output.
The device is entirely command set compatible with the JEDEC 42.4 single-
power-supply Flash standard. Commands are written to the command regis-
ter using standard microprocessor write timing. Register contents serve as
inputs to an internal state-machine that controls the erase and programming
circuitry. Write cycles also internally latch addresses and data needed for the
programming and erase operations. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
Device programming occurs by executing the program command sequence. This
initiates the Write Buffer Programming algorithm - an internal algorithm that
automatically times the program pulse widths and verifies proper cell margin.
This feature provides superior programming performance by grouping locations
being programmed.The Unlock Bypass mode facilitates faster program times
by requiring only two write cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates
the Embedded Erase algorithm - an internal algorithm that automatically pre-
programs the array (if it is not already programmed) before executing the erase
operation. During erase, the device automatically times the erase pulse widths
and verifies proper cell margin.
The Program Suspend/Program Resume feature enables the user to put
program on hold for any period of time to read data from any sector that is not
selected for programming. If a read is needed from the SecSi Sector area (One
Time Program area), Persistent Protection area, Dynamic Protection area, or the
CFI area, after an program suspend, then the user must use the proper com-
mand sequence to enter and exit this region. The program suspend/resume
functionality is also available when programming in erase suspend (1 level depth
only).
The Erase Suspend/Erase Resume feature enables the user to put erase on
hold for any period of time to read data from, or program data to, any sector
that is not selected for erasure. True background erase can thus be achieved. If
a read is needed from the SecSi Sector area (One Time Program area), Persis-
tent Protection area, Dynamic Protection area, or the CFI area, after an erase
suspend, then the user must use the proper command sequence to enter and
exit this region.
The hardware RESET# pin terminates any operation in progress and resets
the internal state machine to reading array data. The RESET# pin may be tied to
the system reset circuitry. A system reset would thus also reset the device, en-
abling the system microprocessor to read boot-up firmware from the Flash
memory device.
The host system can detect whether a program or erase operation is complete
by using the device status bit DQ7 (Data# Polling), DQ6/DQ2 (toggle bits), DQ5
(exceeded timing limit), DQ3 (sector erase timer), and DQ1 (write to buffer
abort). After a program or erase cycle has been completed, the device automat-
ically returns to reading array data.


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