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S71WS512NE0BFWZZ 데이터시트(HTML) 25 Page - SPANSION

부품명 S71WS512NE0BFWZZ
상세내용  Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 1.8 Volt
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S71WS512NE0BFWZZ 데이터시트(HTML) 25 Page - SPANSION

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June 28, 2004 S71WS512NE0BFWZZ_00_A1
S29WSxxxN MirrorBit™ Flash Family For Multi-chip Products (MCP)
25
Ad vance
Info rmat i o n
8-, 16-, and 32-Word Linear Burst with Wrap Around
The remaining three burst read modes are of the linear wrap around design, in
which a fixed number of words are read from consecutive addresses. In each of
these modes, the burst addresses read are determined by the group within which
the starting address falls. The groups are sized according to the number of words
read in a single burst sequence for a given mode (see Table 4.)
For example, if the starting address in the 8-word mode is 39h, the address range
to be read would be 38-3Fh, and the burst sequence would be 39-3A-3B-3C-3D-
3E-3F-38h if wrap around is enabled. The burst sequence begins with the starting
address written to the device, but wraps back to the first address in the selected
group. In a similar fashion, the 16-word and 32-word Linear Wrap modes begin
their burst sequence on the starting address written to the device, and then wrap
back to the first address in the selected address group. Note that in these three
burst read modes the address pointer does not cross the boundary that
occurs every 128 words; thus, no wait states are inserted (except during
the initial access). (See Figure 15)
8-, 16-, and 32-Word Linear Burst without Wrap Around
If wrap around is not enabled, 8-word, 16-word, or 32-word burst will execute
linearly up to the maximum memory address of the selected number of words.
The burst will stop after 8, 16, or 32 addresses and will not wrap around to the
first address of the selected group. For example: if the starting address in the 8-
word mode is 39h, the address range to be read would be 39-40h, and the burst
sequence would be 39-3A-3B-3C-3D-3E-3F-40 if wrap around is not enabled. The
next address to be read will require a new address and AVD# pulse.
The RDY pin indicates when data is valid on the bus.
Configuration Register
The device uses a configuration register to set the various burst parameters:
number of wait states, burst read mode, active clock edge, RDY configuration,
and synchronous mode active. For more information, see Table 16.
Handshaking
The device is equipped with a handshaking feature that allows the host system
to simply monitor the RDY signal from the device to determine when the burst
data is ready to be read. The host system should use the programmable wait
state configuration to set the number of wait states for optimal burst mode oper-
ation. The initial word of burst data is indicated by the rising edge of RDY after
OE# goes low.
For optimal burst mode performance, the host system must set the appropriate
number of wait states in the flash device depending on clock frequency. See the
"Set Configuration Register Command Sequence" section and the "Requirements
for Synchronous (Burst) Read Operation" section for more information.
Table 4. Burst Address Groups
Mode
Group Size
Group Address Ranges
8-word
8 words
0-7h, 8-Fh, 10-17h,...
16-word
16 words
0-Fh, 10-1Fh, 20-2Fh,...
32-word
32 words
00-1Fh, 20-3Fh, 40-5Fh,...


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