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S71WS-N ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 6 Page - SPANSION

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์ƒ์„ธ๋‚ด์šฉ  Stacked Multi-Chip Product (MCP)
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S71WS-N
S71WS-N_00_A6 July 19, 2006
Data
Sheet
(Adv an ce
Inf o r m a t io n)
3.
Input/Output Descriptions
Table 3.1 identifies the input and output package connections provided on the device.
Table 3.1 Input/Output Descriptions
Symbol
Description
A23-A0
Address inputs
DQ15-DQ0
Data input/output
OE#
Output Enable input. Asynchronous relative to CLK for the Burst mode.
WE#
Write Enable input.
VSS
Ground
NC
No Connect; not connected internally
RDY
Ready output. Indicates the status of the Burst read. The WAIT# pin of the pSRAM is tied to RDY.
CLK
Clock input. In burst mode, after the initial word is output, subsequent active edges of CLK increment the internal
address counter. Should be at VIL or VIH while in asynchronous mode
AVD#
Address Valid input. Indicates to device that the valid address is present on the address inputs.
Low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched.
High = device ignores address inputs
F-RST#
Hardware reset input. Low = device resets and returns to reading array data
F-WP#
Hardware write protect input. At VIL, disables program and erase functions in the four outermost sectors. Should be
at VIH for all other conditions.
F-ACC
Accelerated input. At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL,
disables all program and erase functions. Should be at VIH for all other conditions.
R-CE1#
Chip-enable input for pSRAM.
F1-CE#
Chip-enable input for Flash 1. Asynchronous relative to CLK for Burst Mode.
F2-CE#
Chip-enable input for Flash 2. Asynchronous relative to CLK for Burst Mode. This applies to the 512Mb MCP only.
R-CRE
Control Register Enable (pSRAM). For CellularRAM only.
F-VCC
Flash 1.8 Volt-only single power supply.
R-VCC
pSRAM Power Supply.
R-UB#
Upper Byte Control (pSRAM).
R-LB#
Lower Byte Control (pSRAM)
DNU
Do Not Use


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