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89 / 188 page September 15, 2005 S71WS-N_01_A4 S71WS-Nx0 Based MCPs 87 Advance Information Wait State Configuration Register Setup: D13, D12, D11 = “111” ⇒ Reserved D13, D12, D11 = “110” ⇒ Reserved D13, D12, D11 = “101” ⇒ 5 programmed, 7 total D13, D12, D11 = “100” ⇒ 4 programmed, 6 total D13, D12, D11 = “011” ⇒ 3 programmed, 5 total Note: Figure assumes address D0 is not at an address boundary, and wait state is set to “101”. Figure 14.23 Example of Wait States Insertion Data AVD# OE# CLK 12 3 4 5 D0 D1 01 6 2 7 3 total number of clock cycles following addresses being latched Rising edge of next clock cycle following last wait state triggers next burst data number of clock cycles programmed 45 |
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