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S71WS512NC0BAWE70 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 94 Page - SPANSION

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์ƒ์„ธ๋‚ด์šฉ  Stacked Multi-Chip Product (MCP)
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92
S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005
Ad van c e
Inf o rmation
Table 15.1
Memory Array Commands
Command Sequence
(Notes)
Bus Cycles (Notes 1โ€“5)
First
Second
Third
Fourth
Fifth
Sixth
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Asynchronous Read (6)1
RA
RD
Reset (7)
1
XXX
F0
Manufacturer ID
4
555
AA
2AA
55
[BA]555
90
[BA]X00
0001
Device ID (9)
6
555
AA
2AA
55
[BA]555
90
[BA]X01
227E
BA+X0E
Data
BA+X0F 2200
Indicator Bits (10)
4
555
AA
2AA
55
[BA]555
90
[BA]X03
Data
Program
4
555
AA
2AA
55
555
A0
PA
PD
Write to Buffer (11)
6
555
AA
2AA
55
PA
25
PA
WC
PA
PD
WBL
PD
Program Buffer to Flash
1
SA
29
Write to Buffer Abort Reset (12)
3
555
AA
2AA
55
555
F0
Chip Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
Sector Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
SA
30
Erase/Program Suspend (13)
1
BA
B0
Erase/Program Resume (14)
1
BA
30
Set Configuration Register (18)
4
555
AA
2AA
55
555
D0
X00
CR
Read Configuration Register
4
555
AA
2AA
55
555
C6
X00
CR
CFI Query (15)
1
[BA]555
98
Entry
3
555
AA
2AA
55
555
20
Program (16)
2
XXX
A0
PA
PD
CFI (16)
1
XXX
98
Reset
2
XXX
90
XXX
00
Entry
3
555
AA
2AA
55
555
88
Program (17)
4
555
AA
2AA
55
555
A0
PA
PD
Read (17)1
00
Data
Exit (17)
4
555
AA
2AA
55
555
90
XXX
00
Legend:
X = Donโ€™t care.
RA = Read Address.
RD = Read Data.
PA = Program Address. Addresses latch on the rising edge of the
AVD# pulse or active edge of CLK, whichever occurs first.
PD = Program Data. Data latches on the rising edge of WE# or CE#
pulse, whichever occurs first.
SA = Sector Address. WS256N = A23โ€“A14; WS128N = A22โ€“A14.
BA = Bank Address. WS256N = A23โ€“A20; WS128N = A22โ€“A20.
CR = Configuration Register data bits D15โ€“D0.
WBL = Write Buffer Location. Address must be within the same write
buffer page as PA.
WC = Word Count. Number of write buffer locations to load minus 1.
Notes:
1. See Table 10.1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells indicate read cycles.
4. Address and data bits not specified in table, legend, or notes are
donโ€™t cares (each hex digit implies 4 bits of data).
5. Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state.
The system must write the reset command to return the device
to reading array data.
6. No unlock or command cycles required when bank is reading
array data.
7. Reset command is required to return to reading array data (or to
the erase-suspend-read mode if previously in Erase Suspend)
when a bank is in the autoselect mode, or if DQ5 goes high
(while the bank is providing status information) or performing
sector lock/unlock.
8. The system must provide the bank address. See Autoselect
section for more information.
9. Data in cycle 5 is 2230 (WS256N) or 2231 (WS128N).
10. See Table 10.9 for indicator bit values.
11. Total number of cycles in the command sequence is determined
by the number of words written to the write buffer.
12. Command sequence resets device for next command after write-
to-buffer operation.
13. System may read and program in non-erasing sectors, or enter
the autoselect mode, when in the Erase Suspend mode. The
Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
14. Erase Resume command is valid only during the Erase Suspend
mode, and requires the bank address.
15. Command is valid when device is ready to read array data or
when device is in autoselect mode. Address equals 55h on all
future devices, but 555h for WS256N/128N.
16. Requires Entry command sequence prior to execution. Unlock
Bypass Reset command is required to return to reading array
data.
17. Requires Entry command sequence prior to execution. Secured
Silicon Sector Exit Reset command is required to exit this mode;
device may otherwise be placed in an unknown state.
18. Requires reset command to configure the Configuration Register.


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