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33 / 188 page September 15, 2005 S71WS-N_01_A4 S71WS-Nx0 Based MCPs 31 Advance Information 10.3.7 Configuration Register The configuration register sets various operational parameters associated with burst mode. Upon power-up or hardware reset, the device defaults to the asynchronous read mode, and the config- uration register settings are in their default state. The host system should determine the proper settings for the entire configuration register, and then execute the Set Configuration Register command sequence, before attempting burst operations. The configuration register is not reset after deasserting CE#. The Configuration Register can also be read using a command sequence (see Table 15.1). The following list describes the register settings. Table 10.9 Configuration Register Reading the Configuration Table. The configuration register can be read with a four-cycle com- mand sequence. See Table 15.1 for sequence details. Once the data has been read from the configuration register, a software reset command is required to set the device into the correct state. CR Bit Function Settings (Binary) CR15 Set Device Read Mode 0 = Synchronous Read (Burst Mode) Enabled 1 = Asynchronous Read Mode (default) Enabled CR14 Reserved 1 = S29WS256N at 6 or 7 Wait State setting 0 = All others 54 MHz 66 Mhz 80 MHz CR13 Programmable Wait State S29WS128N 01 1 011 = Data valid on 5th active CLK edge after addresses latched 100 = Data valid on 6th active CLK edge after addresses latched 101 = Data valid on 7th active CLK edge after addresses latched (default) 110 = Reserved 111 = Reserved Inserts wait states before initial data is available. Setting greater number of wait states before initial data reduces latency after initial data. (Notes 1, 2) S29WS256N CR12 S29WS128N 10 0 S29WS256N CR11 S29WS128N 10 1 S29WS256N CR10 RDY Polarity 0 = RDY signal active low 1 = RDY signal active high (default) CR9 Reserved 1 = default CR8 RDY 0 = RDY active one clock cycle before data 1 = RDY active with data (default) When CR13-CR11 are set to 000, RDY is active with data regardless of CR8 setting. CR7 Reserved 1 = default CR6 Reserved 1 = default CR5 Reserved 0 = default CR4 Reserved 0 = default CR3 Burst Wrap Around 0 = No Wrap Around Burst 1 = Wrap Around Burst (default) CR2 CR1 CR0 Burst Length 000 = Continuous (default) 010 = 8-Word Linear Burst 011 = 16-Word Linear Burst 100 = 32-Word Linear Burst (All other bit settings are reserved) Notes: 1. Refer to Tables 10.2 - 10.7 for wait states requirements. 2. Refer to Synchronous Burst Read timing diagrams 3. Configuration Register is in the default state upon power-up or hardware reset. |
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