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85 / 188 page September 15, 2005 S71WS-N_01_A4 S71WS-Nx0 Based MCPs 83 Advance Information Note: Use setup and hold times from conventional program operation. Figure 14.16 Accelerated Unlock Bypass Programming Timing Notes: 1. Status reads in figure are shown as asynchronous. 2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is completeData# Polling outputs true data. Figure 14.17 Data# Polling Timings (During Embedded Algorithm) CE# AVD# WE# Addresses Data OE# ACC Don't Care Don't Care A0h Don't Care PA PD VID VIL or VIH t VID t VIDS WE# CE# OE# High Z tOE High Z Addresses AVD# tOEH tCE tCH tOEZ tCEZ Status Data Status Data tACC VA VA Data |
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