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84
S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005
Ad van c e
Inf o rmation
Notes:
1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, .
Figure 14.18 Toggle Bit Timings (During Embedded Algorithm)
Notes:
1. The timings are similar to synchronous read timings.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, .
3. RDY is active with data (D8 = 1 in the Configuration Register). When D8 = 0 in the Configuration Register, RDY is active one clock cycle before
data.
Figure 14.19 Synchronous Data Polling Timings/Toggle Bit Timings
WE#
CE#
OE#
High Z
tOE
High Z
Addresses
AVD#
tOEH
tCE
tCH
tOEZ
tCEZ
Status Data
Status Data
tACC
VA
VA
Data
CE#
CLK
AVD#
Addresses
OE#
Data
RDY
Status Data
Status Data
VA
VA
tIACC
tIACC


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