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S71WS512NC0BAWE33 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 95 Page - SPANSION

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S71WS512NC0BAWE33 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 95 Page - SPANSION

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September 15, 2005 S71WS-N_01_A4
S71WS-Nx0 Based MCPs
93
Advance
Information
Table 15.2 Sector Protection Commands
Command Sequence
(Notes)
Bus Cycles (Notes 1โ€“4)
First
Second
Third
Fourth
Fifth
Sixth
Seventh
Addr
Data
Addr
Data
Addr
Data
Addr
Data Addr Data Addr Data Addr Data
Lock
Register
Bits
Command Set Entry (5)
3
555
AA
2AA
55
555
40
Program (6, 12)
2
XX
A0
77/00
data
Read (6)
1
77
data
Command Set Exit (7)
2
XX
90
XX
00
Password
Protection
Command Set Entry (5)
3
555
AA
2AA
55
555
60
Program [0-3] (8)
2
XX
A0
00
PWD[0-3]
Read (9)4 0...00 PWD0 0...01
PWD1
0...02
PWD2 0...03 PWD3
Unlock
7
00
25
00
03
00
PWD0
01
PWD1
02
PWD2
03
PWD3
00
29
Command Set Exit (7)
2
XX
90
XX
00
Non-Volatile
Sector
Protection (PPB)
Command Set Entry (5)
3
555
AA
2AA
55
[BA]555
C0
PPB Program (10)
2
XX
A0
SA
00
All PPB Erase (10, 11)
2
XX
80
00
30
PPB Status Read
1
SA
RD(0)
Command Set Exit (7)
2
XX
90
XX
00
Global
Volatile Sector
Protection
Freeze
(PPB Lock)
Command Set Entry (5)
3
555
AA
2AA
55
[BA]555
50
PPB Lock Bit Set
2
XX
A0
XX
00
PPB Lock Bit Status Read
1
BA
RD(0)
Command Set Exit (7)
2
XX
90
XX
00
Volatile Sector
Protection
(DYB)
Command Set Entry (5)
3
555
AA
2AA
55
[BA]555
E0
DYB Set
2
XX
A0
SA
00
DYB Clear
2
XX
A0
SA
01
DYB Status Read
1
SA
RD(0)
Command Set Exit (7)
2
XX
90
XX
00
Legend:
X = Donโ€™t care.
RA = Address of the memory location to be read.
PD(0) = Secured Silicon Sector Lock Bit. PD(0), or bit[0].
PD(1) = Persistent Protection Mode Lock Bit. PD(1), or bit[1], must
be set to โ€˜0โ€™ for protection while PD(2), bit[2] must be left as โ€˜1โ€™.
PD(2) = Password Protection Mode Lock Bit. PD(2), or bit[2], must
be set to โ€˜0โ€™ for protection while PD(1), bit[1] must be left as โ€˜1โ€™.
PD(3) = Protection Mode OTP Bit. PD(3) or bit[3].
SA = Sector Address. WS256N = A23โ€“A14; WS128N = A22โ€“A14.
BA = Bank Address. WS256N = A23โ€“A20; WS128N = A22โ€“A20.
PWD3โ€“PWD0 = Password Data. PD3โ€“PD0 present four 16 bit
combinations that represent the 64-bit Password
PWA = Password Address. Address bits A1 and A0 are used to select
each 16-bit portion of the 64-bit entity.
PWD = Password Data.
RD(0), RD(1), RD(2) = DQ0, DQ1, or DQ2 protection indicator bit. If
protected, DQ0, DQ1, or DQ2 = 0. If unprotected, DQ0, DQ1,
DQ2 = 1.
Notes:
1. All values are in hexadecimal.
2. Shaded cells indicate read cycles.
3. Address and data bits not specified in table, legend, or notes are
donโ€™t cares (each hex digit implies 4 bits of data).
4. Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state.
The system must write the reset command to return the device
to reading array data.
5. Entry commands are required to enter a specific mode to enable
instructions only available within that mode.
6. If both the Persistent Protection Mode Locking Bit and the
Password Protection Mode Locking Bit are set at the same time,
the command operation aborts and returns the device to the
default Persistent Sector Protection Mode during 2nd bus cycle.
Note that on all future devices, addresses equal 00h, but is
currently 77h for the WS256N only. See Tables 11.1 and 11.2 for
explanation of lock bits.
7. Exit command must be issued to reset the device into read
mode; device may otherwise be placed in an unknown state.
8. Entire two bus-cycle sequence must be entered for each portion
of the password.
9. Full address range is required for reading password.
10. See Figure 11.2 for details.
11. โ€œAll PPB Eraseโ€ command pre-programs all PPBs before erasure
to prevent over-erasure.
12. The second cycle address for the lock register program operation
is 77 for S29WS256N; however, for WS128N this address is 00.


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