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74
S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005
Ad van c e
Inf o rmation
14.8.3
Timing Diagrams
Notes:
1. Figure shows total number of wait states set to five cycles. The total number of
wait states can be programmed from two cycles to seven cycles.
2. If any burst address occurs at โ€œaddress + 1โ€, โ€œaddress + 2โ€, or โ€œaddress + 3โ€,
additional clock delay cycles are inserted, and are indicated by RDY.
3. The device is in synchronous mode.
Figure 14.7 CLK Synchronous Burst Mode Read
Da
Da + 1
Da + n
OE#
Data (n)
Addresses
Aa
AVD#
RDY (n)
CLK
CE#
tCES
tACS
tAVC
tAVD
tACH
tOE
tRACC
tOEZ
tCEZ
tIACC
tBDH
5 cycles for initial access shown.
18.5 ns typ. (54 MHz)
Hi-Z
Hi-Z
Hi-Z
12
3
4
5
6
7
tRDYS
tBACC
Da + 3
Da + 2
Da
Da + 1
Da + n
Data (n + 1)
RDY (n + 1)
Hi-Z
Hi-Z
Hi-Z
Da + 2
Da + 2
Da
Da + 1
Da + n
Data (n + 2)
RDY (n + 2)
Hi-Z
Hi-Z
Hi-Z
Da + 1
Da + 1
Da
Da
Da + n
Data (n + 3)
RDY (n + 3)
Hi-Z
Hi-Z
Hi-Z
Da
Da
tCR


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