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S71WS512NC0BFWE73 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 87 Page - SPANSION

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์ƒ์„ธ๋‚ด์šฉ  Stacked Multi-Chip Product (MCP)
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S71WS512NC0BFWE73 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 87 Page - SPANSION

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September 15, 2005 S71WS-N_01_A4
S71WS-Nx0 Based MCPs
85
Advance
Information
Notes:
1. RDY(1) active with data (D8 = 1 in the Configuration Register).
2. RDY(2) active one clock cycle before data (D8 = 0 in the Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60.
4. Figure shows the device not crossing a bank in the process of performing an erase or program.
5. RDY does not go low and no additional wait states are required for WS โ‰ค 5.
Figure 14.21 Latency with Boundary Crossing when Frequency > 66 MHz
Enter
Erase
Erase
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase Suspend
Read
Erase
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Suspend
Program
Resume
Embedded
Erasing
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#
to toggle DQ2 and DQ6.
Figure 14.20 DQ2 vs. DQ6
CLK
Address (hex)
C124
C125
C126
C127
C127
C128
C129
C130
C131
D124
D125
D126
D127
D128
D129
D130
(stays high)
AVD#
RDY(1)
Data
OE#,
CE#
(stays low)
Address boundary occurs every 128 words, beginning at address
00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
7C
7D
7E
7F
7F
80
81
82
83
latency
RDY(2)
latency
tRACC
tRACC
tRACC
tRACC


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