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S71WS512NC0BFWE73 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 18 Page - SPANSION

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์ƒ์„ธ๋‚ด์šฉ  Stacked Multi-Chip Product (MCP)
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S71WS512NC0BFWE73 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 18 Page - SPANSION

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16
S71WS-Nx0 Based MCPs
S71WS-N_01_A4 September 15, 2005
Ad van c e
Inf o rmation
5.2.2
Look-Ahead Connection Diagram
Notes:
Ball
3.0 V VCC
1.8 V VCC
1. In a 3.0V system, the GL device used as Data has to have WP tied to VCC
2. F1 and F2 denote XIP/Flash, F3 and F4 denote Data/Companion Flash
D2
NC
F-WP#
D5
WP#/ACC
ACC
F5
RY/BY
F-RDY/R-WAIT#
Legend:
xRAM Shared
pSRAM Only
Flash/xRAM
Shared
Flash/Data
Shared
RFU
(Reserved for
Future Use)
Code Flash Only
X
MirrorBit Data
Only
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RFU
B1
B10
RFU
B2
RFU
B9
RFU
F-DQS0
N1
N1
F-DQS1
N10
RFU
N2
RFU
N9
RFU
P1
RFU
P10
P2
RFU
RFU
P9
A1
RFU
RFU
A10
RFU
A2
RFU
A9
D3
A7
ACC
D5
R-LB#
D4
D7
A8
WP#
D2
D8
A11
F3-CE#
D9
D6
WE#
F3
F3
A5
F5
RDY/WAIT#
F4
F4
A18
F7
F7
A9
F2
F2
A2
F8
F8
A13
F9
F9
A21
F6
F6
A20
J3
OE#
J5
DQ3
J4
DQ9
J7
DQ13
F1-CE#
J2
J8
DQ15
R-CRE or
R-MRS
J9
J6
DQ4
L3
L3
DQ8
L5
L5
DQ11
L4
L4
DQ2
L7
L7
DQ5
R-VCC
L2
L8
L8
DQ14
WP#
L9
L6
L6
A25
C3
VSS
F2-CE#
C5
C4
CLK
F-CLK#
C7
AVD#
C2
R-OE#
C8
F2-OE#
C9
F-VCC
C6
C6
C6
C6
E3
A6
F-RST#
C7
R-UB#
D4
E7
A19
E2
A3
E8
A12
E9
A15
R1-CE2
E6
A4
G3
G3
R2-CE1
G5
A17
G4
G4
A10
G7
G7
A1
G2
G2
A14
G8
G8
A22
G9
G9
A23
G6
G6
H3
H3
VSS
R2-VCC
H5
H4
H4
DQ1
H7
DQ6
H2
H2
A0
H8
A24
H9
A16
R2-CE2
H6
DQ0
K3
K3
F-VCC
K5
DQ10
K4
K4
K7
K7
DQ12
R1-CE1#
K2
DQ7
K8
K8
K9
K9
VSS
R1-VCC
E6
M3
A26
F-VCC
M5
M4
VSS
R-VCCQ
M7
M2
A27
F-VCCQ
M8
R-CLK#
M9
F4-CE#
M6


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