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์ƒ์„ธ๋‚ด์šฉ  Stacked Multi-Chip Product (MCP)
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September 15, 2005 S71WS-N_01_A4
S71WS-Nx0 Based MCPs
21
Advance
Information
6
Input/Output Descriptions & Logic Symbol
Table 6.1 identifies the input and output package connections provided on the device.
Table 6.1 Input/Output Descriptions
Symbol
Type
Description
A23โ€“A0
Input
Address lines for WS256N (A22-A0 for WS128).
DQ15โ€“DQ0
I/O
Data input/output.
CE#
Input
Chip Enable. Asynchronous relative to CLK.
OE#
Input
Output Enable. Asynchronous relative to CLK.
WE#
Input
Write Enable.
VCC
Supply
Device Power Supply.
VSS
I/O
Ground.
NC
No Connect
Not connected internally.
RDY
Output
Ready. Indicates when valid burst data is ready to be read.
CLK
Input
Clock Input. In burst mode, after the initial word is output, subsequent active edges of CLK
increment the internal address counter. Should be at VIL or VIH while in asynchronous
mode.
AVD#
Input
Address Valid. Indicates to device that the valid address is present on the address inputs.
When low during asynchronous mode, indicates valid address; when low during burst
mode, causes starting address to be latched at the next active clock edge.
When high, device ignores address inputs.
RESET#
Input
Hardware Reset. Low = device resets and returns to reading array data.
WP#
Input
Write Protect. At VIL, disables program and erase functions in the four outermost sectors.
Should be at VIH for all other conditions.
ACC
Input
Acceleration Input. At VHH, accelerates programming; automatically places device in
unlock bypass mode. At VIL, disables all program and erase functions. Should be at VIH for
all other conditions.
RFU
Reserved
Reserved for future use (see MCP look-ahead pinout for use with MCP).


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