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전자부품 데이터시트 검색엔진 |
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S29PL129N65FAI000 데이터시트(PDF) 24 Page - SPANSION |
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S29PL129N65FAI000 데이터시트(HTML) 24 Page - SPANSION |
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24 / 85 page  22 S29PL-N MirrorBit™ Flash Family S29PL-N_00_A4 November 23, 2005 Preliminary Legend: L = Logic Low = VIL, H = Logic High = VIH,VID = 11.5–12.5 V, VHH = 8.5 – 9.5 V, X = Don’t Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. The sector and sector unprotect functions may also be implemented by programming equipment. 2. WP#/ACC must be high when writing to the upper two and lower two sectors. 7.2 Asynchronous Read The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register con- tents are altered. 7.2.1 Non-Page Random Read Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from the stable addresses and stable CE# to valid data at the output inputs. The output enable access time is the delay from the falling edge of the OE# to valid data at the output (assuming the addresses have been stable for at least tACC – tOE time). 7.2.2 Page Mode Read The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. The random or initial page access is tACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to tPACC. When CE# is deasserted (= VIH), the reassertion of CE# for subsequent access has access time of tACC or tCE. Here again, CE# selects the device and OE# is the output control and should be used to gate data to the output inputs if the device is selected. Fast page mode accesses are obtained by keeping Amax – A3 constant and changing A2 – A0 to select the specific word within that page. Address bits Amax – A3 select an 8-word page, and address bits A2 – A0 select a specific word within that page. This is an asynchronous operation with the microprocessor supplying the specific word location. See Table 7.3 for details on selecting specific words. Table 7.2 Dual Chip Enable Device Operation Operation CE1# CE2# OE# WE# RESET# WP#/ACC Addresses (A21 – A0) DQ15 – DQ0 Read LH LH H X AIN DOUT HL Write LH HL H X (Note 2) AIN DIN HL Standby H H X X H X X High-Z Output Disable L L H H H X X High-Z Reset X X X X L X X High-Z Temporary Sector Unprotect (High Voltage) XX X X VID X AIN DIN |
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