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FM8P51
Rev1.2 Mar 15, 2005
P.6/FM8P51
FEELING
TECHNOLOGY
1.2 Data Memory Organization
Data memory is composed of Special Function Registers and General Purpose Registers.
The General Purpose Registers are accessed either directly or indirectly through the FSR register.
The Special Function Registers are registers used by the CPU and peripheral functions to control the
operation of the device.
In FM8P51 series, the data memory is partitioned into four banks. Switching between these banks requires the RP1
and RP0 bits in the FSR register to be configured for the desired bank.
TABLE 1.1: Registers File Map for FM8P51 Series
Description
FSR<7:6>
Address
0 0
Bank 0
0 1
Bank 1
1 0
Bank 2
1 1
Bank 3
00h
INDF
01h
TMR0
02h
PCL
N/A
OPTION
03h
STATUS
04h
FSR
05h
PORTA
05h
IOSTA
06h
PORTB
06h
IOSTB
07h
PORTC
07h
IOSTC
08h
PORTD
08h
IOSTD
09h
PORTE
Memory back to address in Bank 0
09h
IOSTE
0Ah
SPIRCB
T23CON
PWMCON
RFCCON
0Bh
SPITXB
TMR2
PW0DCL
RFCDL
0Ch
SPISTAT
PR2
PW0DCH
RFCDH
0Ch
T1CON
0Dh
SPICON
TMR3
PW1DCL
CMPDX
0Dh
PHCON
0Eh
TMR1
PR3
PW1DCH
CMPDY
0Eh
PCON
0Fh
PR1
CMPSTAT
0Fh
INTEN
10h
|
1Fh
General
Purpose
Registers
Memory back to address in Bank 0
20h
|
3Eh
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
3Fh
INTFLAG
Memory back to address in Bank 0
TABLE 1.2: The Registers Controlled by OPTION/OPTIONR or IOST/IOSTR Instructions
Address
Name
B7
B6
B5
B4
B3
B2
B1
B0
Unbanked
N/A (r/w)
OPTION
/PHBCE
GIE
PSA
PS2
PS1
PS0
05h (r/w)
IOSTA
Port A I/O Control Register
06h (r/w)
IOSTB
Port B I/O Control Register
07h (r/w)
IOSTC
Port C I/O Control Register
08h (r/w)
IOSTD
Port D I/O Control Register
09h (r/w)
IOSTE
Port E I/O Control Register
0Ch (r/w)
T1CON
T1ON
T1P1
T1P0
0Dh (r/w)
PHCON
HDC
/PHE
/PHD
/PHB
/PHA
0Eh (r/w)
PCON
LVDTE
ODE
WDTE
-
ROC
-
-
/WUE
0Fh (r/w)
INTEN
SPITXIE
RFCIE
T3IE
T2IE
T1IE
SPIRCIE
INTIE
T0IE
Legend: - = unimplemented, read as ‘0’, * = unimplemented, read as ‘1’.