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TMPR4927ATB-200 데이터시트(PDF) 5 Page - Toshiba Semiconductor

부품명 TMPR4927ATB-200
부품 상세설명  TOSHIBA RISC PROCESSOR
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제조업체  TOSHIBA [Toshiba Semiconductor]
홈페이지  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4927ATB-200 데이터시트(HTML) 5 Page - Toshiba Semiconductor

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INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4927ATB-200
EJC-TMPR4927ATB-5
17 / Jan / 02
TOSHIBA CORPORATION
2.5 TX4927 Peripheral Circuit FEATURES
n External Bus Controller ( EBUSC )
The External Bus Controller generates necessary signals to control external memory and I/O
devices.
• 8 channels of chip select signals, enabling control of up to eight devices
• Supports access to ROM ( including mask ROM, page mode ROM, EPROM and
EEPROM), SRAM, flash ROM, and I/O devices
• Supports 32-bit, 16-bit and 8-bit data bus sizing on a per channel basis
• Supports selection among full speed (uo to 100MHz ), 1/2 speed ( up to 50MHz), 1/3
speed ( uo tp 33MHz ) and 1/4 speed ( up to 25MHz) on a per channel basis
• Support specification of timing on a per channel basis
• The user can specify setup and hold times for address, chip enable, write enable, and
output enable signals
• Supports memory sizes of 1M byte to 1G byte for devices with 32-bit data bus, 1M byte
to 512M bytes for devices with 16-bit data bus, and 1M byte to 256M bytes for devices
with 8-bit data bus
n DMA Controller ( DMAC )
The TX4927 contains a 4-channel DMA controller that executes DMA transfer to memory
and I/O devices.
• 4-channel independently handling internal / external DMA requests
• Supports DMA transfer with built-in serial I/O controller and AC-link controller based on
internal DMA requests
• Supports signal address ( fly-by DMA ) and dual address transfers in external I/O DMA
transfer mode using external DMA requests
• Supports transfer between memory and external I/O devices having 32 / 16 / 8-bit data
bus
• Supports memory-to-memory copy mode, with no address boundary restrictions
• Supports burst transfer of up to 8 double words for a single read / write
• Supports memory fill mode, writing double-word data to specified memory area
• Supports chained DMA transfer


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