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ZL50062 데이터시트(PDF) 44 Page - Zarlink Semiconductor Inc |
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ZL50062 데이터시트(HTML) 44 Page - Zarlink Semiconductor Inc |
44 / 68 page ZL50062/4 Data Sheet 44 Zarlink Semiconductor Inc. 13.4 Backplane Input Bit Delay Registers (BIDR0 to BIDR31) Addresses 0063H to 0082H There are thirty-two Backplane Input Delay Registers (BIDR0 to BIDR31). When the SMPL_MODE bit in the Control Register is LOW, the input data sampling point defaults to the 3/4 bit location and BIDR0 to BIDR31 define the input bit and fractional bit delay of each Backplane stream. The possible bit delay adjustment is up to 73/4 bits, in steps of 1/ 4 bit. When the SMPL_MODE bit is HIGH, BIDR0 to BIDR31 define the input bit sampling point as well as the integer bit delay of each Backplane stream. The input bit sampling point can be adjusted in 1/4 bit increments. The bit delay can be adjusted in 1-bit increments from 0 to 7 bits. The BIDR0 to BIDR31 registers are configured as follows: Table 17 - Backplane Input Bit Delay Register (BIDRn) Bits 11100 7 7 3/4 11101 7 1/4 7 4/4 11110 7 1/2 7 1/4 11111 7 3/4 7 2/4 BIDRn Bit (where n = 0 to 31) Name Reset Value Description 15:5 Reserved 0 Reserved Must be set to 0 for normal operation 4:0 BID[4:0] 0 Backplane Input Bit Delay Register When SMPL_MODE = LOW, the binary value of these bits refers to the input bit and fractional bit delay value (0 to 73/4). When SMPL_MODE = HIGH, the binary value of BID[1:0] refers to the input bit sampling point (1/4 to 4/ 4). BID[4:2] refer to the integer bit delay value (0 to 7 bits). LIDn SMPL_MODE = LOW SMPL_MODE = HIGH LID4 LID3 LID2 LID1 LID0 Input Data Bit Delay Input Data Bit Delay Input Data Sampling Point Table 16 - Local Input Bit Delay and Sampling Point Programming Table (continued) |
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유사한 설명 - ZL50062 |
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