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AD1939XSTZ 데이터시트(PDF) 11 Page - Analog Devices |
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AD1939XSTZ 데이터시트(HTML) 11 Page - Analog Devices |
11 / 30 page Preliminary Technical Data AD1935/AD1936/AD1937/AD1938/AD1939 Rev. Pr I | Page 11 of 30 R/ W 0 SCK SDA 0 0 0 1 AD1 AD0 0 0 0 0 0 1 1 0 ACK. BY AD193X START BY MASTER D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY AD193X STOP BY MASTER SCK (CONTINUED) SDA (CONTINUED) FRAME 1 CHIP ADDRESS BYTE FRAME 3 DATA BYTE TO AD193X FRAME 2 REGISTER ADDRESS BYTE ACK. BY AD193X Figure 11. Format of I2C Write R/ W 0 SCL SDA 0 0 0 1 AD1 AD0 0 0 0 0 0 1 1 0 ACK. BY AD193X START BY MASTER D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY AD193X STOP BY MASTER FRAME 1 CHIP ADDRESS BYTE FRAME 2 REGISTER ADDRESS BYTE ACK. BY AD193X R/ W 0 SCL (Continued) SDA (Continued) 00 0 1 AD1 AD0 REPEATED START BY MASTER FRAME 3 CHIP ADDRESS BYTE FRAME 4 REGISTER DATA ACK. BY AD193X Figure 12. Format of I2C Read Power Supply and Voltage Reference The AD193X is designed for 3.3 V supplies. Separate power supply pins are provided for the analog and digital sections. These pins should be bypassed with 100 nF ceramic chip capacitors, as close to the pins as possible, to minimize noise pickup. A bulk aluminum electrolytic capacitor of at least 22 µF should also be provided on the same PC board as the codec. For critical applications, improved performance will be obtained with separate supplies for the analog and digital sections. If this is not possible, it is recommended that the analog and digital supplies be isolated by means of a ferrite bead in series with each supply. It is important that the analog supply be as clean as possible. The AD1935 (64-pin single-ended version), and the AD1939 and AD1937 (64-pin differential versions) include a 3.3V regulator driver which requires only an external pass transistor and bypass capacitors to make a 5V to 3.3V regulator. If the regulator driver is not used, VSUPPLY, VDRIVE, and VSENSE should be connected to DGND. All digital inputs are compatible with TTL and CMOS levels. All outputs are driven from the 3.3 V DVDD supply and are compatible with TTL and 3.3 V CMOS levels. The ADC and DAC internal voltage reference VREF is brought out on FILTR and should be bypassed as close as possible to the chip, with a parallel combination of 10 µF and 100 nF. Any external current drawn should be limited to less than 50 µA. The internal reference can be disabled in PLL and Clock Control Register 1 and FILTR driven from an external source. This can be used to scale the DAC output to a power amplifier's clipping level based on its power supply voltage. The ADC input gain will also vary by the inverse ratio. The total gain from ADC input to DAC output will stay constant. The CM pin is the internal common-mode reference. It should be bypassed as close as possible to the chip, with a parallel combination of 10 µF and 100 nF. This voltage may be used to bias external op amps to the common-mode voltage of the input and output signal pins. The output current should be limited to less than 0.5 mA source and 2 mA sink. |
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