Preliminary Technical Data

AD7765

Rev. PrC | Page 9 of 21

Pin

Number

Pin Mnemonic

Description

12

SDO

Serial Data Out. Address, Status and Data bits are clocked out on this line during each serial

transfer. Each bit is clocked out on an SCO rising edge and valid on the falling edge. See the

AD7765 Interface section for further details.

13

SDI

Serial Data In. The first data bit (MSB) must be valid on the next SCO falling edge after the FSI

event has been latched. 32 bits are required for each write; the first 16-bit word contains the

device and register address and the second word contains the data. See the AD7765 Interface

section for further details.

14

FSI

Frame Sync In. The status of this pin is checked on the falling edge of SCO. If this pin is low then

the first data bit is latched in on the next SCO falling edge. See the AD7765 Interface section

for further details.

15

SYNC

Synchronization Input. A falling edge on this pin resets the internal filter. This can be used to

synchronize multiple devices in a system. See the AD7765 Interface section for further details.

16

RESET/PWDN

When a logic low is sensed on this pin, the part is powered down and all internal circuitry is

reset.

19

MCLK

Master Clock Input. A low jitter digital clock must be applied to this pin. The output data rate

will depend on the frequency of this clock. See Clocking the AD7765 Section for more details.

18

DEC_RATE

This pin selects which of the two decimation modes the AD7765 operates. When logic high is

applied to this pin, decimate by 128 mode is selected. Decimate by 256 is selected when by

applying logic low to the pin.