전자부품 데이터시트 검색엔진 |
|
AD9882AKSTZ-140 데이터시트(PDF) 8 Page - Analog Devices |
|
AD9882AKSTZ-140 데이터시트(HTML) 8 Page - Analog Devices |
8 / 40 page AD9882A Rev. 0 | Page 8 of 40 Pin Type Mnemonic Function Value Pin Number Interface Data Outputs RED [7:0] Outputs of Converter Red, Bit 7 is the MSB 3.3 V CMOS 92–99 Both GREEN [7:0] Outputs of Converter Green, Bit 7 is the MSB 3.3 V CMOS 2–9 Both BLUE [7:0] Outputs of Converter Bue, Bit 7 is the MSB 3.3 V CMOS 12–19 Both Data Clock Output DATACK Data Output Clock for the Analog and Digital Interface 3.3 V CMOS 85 Both RX0+ Digital Input Channel 0 True 33 Digital Digital Video Data Inputs RX0– Digital Input Channel 0 Complement 32 Digital RX1+ Digital Input Channel 1 True 36 Digital RX1– Digital Input Channel 1 Complement 35 Digital RX2+ Digital Input Channel 2 True 39 Digital RX2– Digital Input Channel 2 Complement 38 Digital RXC+ Digital Data Clock True 41 Digital Digital Video Clock Inputs RXC– Digital Data Clock Complement 42 Digital Data Enable DE Data Enable 3.3 V CMOS 86 Digital Control Bits CTL [0:3] Decoded Control Bits 3.3 V CMOS 22–25 Digital RTERM RTERM Sets Internal Termination Resistance 28 Digital HDCP DDCSCL HDCP Slave Serial Port Data Clock 3.3 V CMOS 53 Digital DDCSDA HDCP Slave Serial Port Data I/O 3.3 V CMOS 54 Digital MCL HDCP Master Serial Port Data Clock 3.3 V CMOS 81 Digital MDA HDCP Master Serial Port Data I/O 3.3 V CMOS 82 Digital PIN DESCRIPTIONS OF SHARED PINS BETWEEN ANALOG AND DIGITAL INTERFACES HSOUT—Horizontal Sync Output A reconstructed and phase-aligned version of the video Hsync. The polarity of this output can be controlled via a serial bus bit. In analog interface mode, the placement and duration are variable. In digital interface mode, the placement and duration are set by the graphics transmitter. VSOUT—Vertical Sync Output The separated Vsync from a composite signal or a direct pass- through of the Vsync input. The polarity of this output can be controlled via a serial bus bit. The placement and duration in all modes is set by the graphics transmitter. SERIAL PORT (2-WIRE) SDA—Serial Port Data I/O SCL—Serial Port Data Clock A0—Serial Port Address Input For a full description of the 2-wire serial register, refer to the 2-Wire Serial Control Register Detail section. DATA OUTPUTS RED—Data Output, Red Channel GREEN—Data Output, Green Channel BLUE—Data Output, Blue Channel The main data outputs. Bit 7 is the MSB. These outputs are shared between the two interfaces and behave in accordance with the active interface. Refer to the Analog Interface and Digital Interface sections. DATACK—Data Output Clock Just like the data outputs, the data clock output is shared between the two interfaces. It behaves differently depending on which interface is active. Refer to the DATACK—Data Output Clock section to determine how this pin behaves. . |
유사한 부품 번호 - AD9882AKSTZ-140 |
|
유사한 설명 - AD9882AKSTZ-140 |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |