4

DS563RD1

CRD5381

1. SYSTEM OVERVIEW

1.1

Sample Clock Domain

1.1.1

CS8421 Input Operational Mode

Serial Audio Interface - Left-Justified. The selection of the serial audio interface format is arbitrary, assuming

the serial input format of the CS8421 is in agreement with the serial output format of the CS5381. The se-

lection of the serial audio format is done by connecting a resistor (1.96 k

Ω in this application) to either ground

or the VL supply.

System Clocking - Master mode, LRCK = MCLK/128. In this mode, the CS8421 generates the Serial and

Left/Right clocks within the sampling clock domain. This mode is selected by the resistor connected to the

MS_SEL pin of the CS8421. In this application the MS_SEL pin is connected to ground (equivalent to con-

necting a 1 k

Ω resistor to ground).

1.1.2

CS5381 Operational Mode

Serial Audio Interface - Left-Justified. The selection of the serial audio interface format is arbitrary, assuming

the input format of the CS8421 is in agreement with the output format of the CS5381.

System Clocking - Slave mode. In this application the CS8421 generates the serial and Left/Right clocks

within the sampling clock domain.

Operational Mode or Sample Rate Range - Configured for Quad-Speed Mode to support sample rates

above 100 kHz.

High Pass Filter - Enabled

Master Clock Divide - Enabled to divide the master clock by 2.

1.1.3

Master Clock Frequency Generation

The CS8421 uses the clock supplied through its XTI pin as its master clock (MCLK). The CS5381 also uses

this signal as its master clock (through the MCLK pin). Alternatively, the CS8421 can generate a master

clock (via the MCLK_OUT pin) by connecting a crystal across its XTI-XTO pins, which can supply a MCLK

to the CS5381.

In this application, MCLK_OUT pin is not being used and is pulled high through a 47 k

Ω resistor to VL to

disable it. If a crystal is not being used, as with the crystal oscillator in this application, XTO should be left

unconnected or pulled low through a 47 k

1.1.4

Maximum Sample Rate

The maximum sample rate is limited by the maximum allowable master clock frequency of the CS8421,

which is 27 MHz. The sample rate is this clock frequency divided by 128. This corresponds to a maximum

sample rate of 210.937 kHz within the sample clock domain. In this application, we have chosen a master

clock frequency of 25 MHz, which corresponds to a sample rate of approximately 195.312 kHz

1.1.5

Synchronization of Multiple Sections

In this application multiple CS8421 inputs are set to master mode, and it is important that their serial ports

be aligned in time, with minimum possible phase error. To achieve this, their reset signals are tied together

and routed for minimum skew. The amount of deviation between ILRCKs generated by the respective parts

is typically either 0 or 1 master clock period, or between 0 and 40 ns.