์ „์ž๋ถ€ํ’ˆ ๋ฐ์ดํ„ฐ์‹œํŠธ ๊ฒ€์ƒ‰์—”์ง„
  Korean  โ–ผ

Delete All
ON OFF
ALLDATASHEET.CO.KR

X  

Preview PDF Download HTML

LT1977 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 6 Page - Linear Technology

๋ถ€ํ’ˆ๋ช… LT1977
์ƒ์„ธ๋‚ด์šฉ  High Voltage 1.5A, 500kHz Step-Down Switching Regulator with 100uA Quiescent Current
Download  24 Pages
Scroll/Zoom Zoom In 100% Zoom Out
์ œ์กฐ์‚ฌ  LINER [Linear Technology]
ํ™ˆํŽ˜์ด์ง€  http://www.linear.com
Logo 

LT1977 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 6 Page - Linear Technology

Zoom Inzoom in Zoom Outzoom out
/ 24 page
 6 / 24 page
background image
LT1977
6
1977f
PI FU CTIO S
NC (Pins 1, 3, 5): No Connection.
SW (Pin 2): The SW pin is the emitter of the on-chip power
NPN switch. This pin is driven up to the input pin voltage
during switch on time. Inductor current drives the SW pin
negative during switch off time. Negative voltage is clamped
with the external catch diode. Maximum negative switch
voltage allowed is โ€“0.8V.
VIN (Pin 4): This is the collector of the on-chip power NPN
switch. VIN powers the internal control circuitry when a
voltage on the BIAS pin is not present. High di/dt edges
occur on this pin during switch turn on and off. Keep the
path short from the VIN pin through the input bypass
capacitor, through the catch diode back to SW. All trace
inductance on this path will create a voltage spike at switch
off, adding to the VCE voltage across the internal NPN.
BOOST (Pin 6): The BOOST pin is used to provide a drive
voltage, higher than the input voltage, to the internal
bipolar NPN power switch. Without this added voltage, the
typical switch voltage loss would be about 1.5V. The
additional BOOST voltage allows the switch to saturate
and its voltage loss approximates that of a 0.2โ„ฆ FET
structure.
CT (Pin 7): A capacitor on the CT pin determines the amount
of delay time between the PGFB pin exceeding its thresh-
old (VPGFB) and the PG pin set to a high impedance state.
When the PGFB pin rises above VPGFB, current is sourced
from the CT pin into the external capacitor. When the volt-
age on the external capacitor reaches an internal clamp
(VCT), the PG pin becomes a high impedance node. The
resultant PG delay time is given by t = CCT โ€ข VCT/ICT. If the
TYPICAL PERFOR A CE CHARACTERISTICS
No Load 1A Step Response
Step Response
Burst Mode Operation
Burst Mode Operation
VOUT
20mV/DIV
ISW
500mA/DIV
VIN = 12V
VOUT = 3.3V
IQ = 100ยตA
2ยตs/DIV
1977 G15
VOUT
50mV/DIV
IOUT
500mA/DIV
VIN = 12V
VOUT = 3.3V
COUT = 100ยตF
IDC = 0mA
500ยตs/DIV
1977 G17
VOUT
50mV/DIV
IOUT
500mA/DIV
VIN = 12V
VOUT = 3.3V
COUT = 100ยตF
IDC = 350mA
500ยตs/DIV
1977 G18
VOUT
20mV/DIV
ISW
500mA/DIV
VIN = 12V
VOUT = 3.3V
IQ = 100ยตA
5ms/DIV
1977 G14


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24 


๋ฐ์ดํ„ฐ์‹œํŠธ Download




๋งํฌ URL



Privacy Policy
ALLDATASHEET.CO.KR
ALLDATASHEET ๊ฐ€ ๊ท€ํ•˜์— ๋„์›€์ด ๋˜์…จ๋‚˜์š”?  [ DONATE ]  

Alldatasheet๋Š”?   |   ๊ด‘๊ณ ๋ฌธ์˜    |   ์šด์˜์ž์—๊ฒŒ ์—ฐ๋ฝํ•˜๊ธฐ   |   ๊ฐœ์ธ์ •๋ณด์ทจ๊ธ‰๋ฐฉ์นจ   |   ์ฆ๊ฒจ์ฐพ๊ธฐ   |   ๋งํฌ๊ตํ™˜   |   ์ œ์กฐ์‚ฌ๋ณ„ ๊ฒ€์ƒ‰
All Rights Reservedยฉ Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn