전자부품 데이터시트 검색엔진 |
|
DS4201 데이터시트(PDF) 9 Page - Dallas Semiconductor |
|
DS4201 데이터시트(HTML) 9 Page - Dallas Semiconductor |
9 / 24 page DS4201 9 of 24 102099 isochronous data input with adaptive synchronization. Except for ALT–0, the DS4201 supports 44.1 KHz and 48.0 KHz audio data sampling rates at Endpoint 1. Sampling rate control is performed using ADC standard requests as described in APPENDIX A. PCM data formats are listed in APPENDIX B. ENDPOINT 1 The USB isochronous data pipe at Endpoint 1, EP1, delivers PCM audio data to the DS4201. The data sampling frequency at EP1 can be set at either 44.1 KHz or 48.0 KHz. PCM data captured by the host at rates other than these two rates require sample rate conversion before being sent to the DS4201. Control of the sampling rate is performed with ADC endpoint commands as described in APPENDIX A. The USB isochronous audio data received at EP1 is delivered to Input Terminal 1 (IT:TID1) in the CONTROL interface. There is a one–to–one link between these two elements. The maximum packet size supported by EP1 varies with the PCM data type selected. The maximum packet sizes reported in the STREAMING interface descriptors corresponds to the PCM data format at a 48 KHz sampling rate plus an additional data sample for synchronization. The USB core specification requires a minimum 1 frame delay before a USB device can operate on isochronous data. The DS4201 produces a 1 frame delay and incorporates enough FIFO register storage space for 2 frames total (previous frame plus current frame). ENDPOINT 2 For alternate settings 1–4, the DS4201 uses the asynchronous type of communication synchronization for the isochronous data pipe as defined in the USB core specification. The isochronous synchronization pipe from Endpoint 2 is used to provide the 3–byte data rate feedback value to the host. USB TRANSCEIVER Integrated within the DS4201 is a USB compliant bus transceiver. To comply with USB cable termination requirements, resistors external to the DS4201 must be installed as shown in Figure 4. The 24 ohm, 1% tolerance resistors are necessary to bring the total steady state resistance of each driver to the 28–43 ohms range required by the USB core specification. The 1.5K ohms pull–up resistor is required to identify the bus as high speed USB. TRANSCEIVER TERMINATION Figure 4 VOLTAGE REFERENCE The VREFI input is a connection to a filter node of the internal voltage reference and is used to apply additional filtering of the reference to reduce noise. This is accomplished by connecting both a 0.1 µF and 10 µF capacitor across this input and analog ground. No other connection should be made to this input and the potential for coupling onto this input should be minimized to avoid degrading analog performance. |
유사한 부품 번호 - DS4201 |
|
유사한 설명 - DS4201 |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |