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IDT74ALVCH374 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 2 Page - Integrated Device Technology

๋ถ€ํ’ˆ๋ช… IDT74ALVCH374
์ƒ์„ธ๋‚ด์šฉ  3.3V CMOS OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS AND BUS-HOLD
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์ œ์กฐ์‚ฌ  IDT [Integrated Device Technology]
ํ™ˆํŽ˜์ด์ง€  http://www.idt.com
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IDT74ALVCH374 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 2 Page - Integrated Device Technology

   
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IDT74ALVCH374
3.3VCMOSOCTALPOSITIVEEDGE-TRIGGEREDD-TYPE
1998 Integrated Device Technology, Inc.
DSC-123456
c
FUNCTION TABLE (each flip=flop) (1)
PIN DESCRIPTION
NOTE:
1. As applicable to the device type.
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATING(1)
CAPACITANCE (TA = +25ยฐC, f = 1.0MHz)
SSOP/ TVSOP/ TSSOP/ QSOP
TOP VIEW
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.
Symbol
Parameter(1)
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
5
7
pF
COUT
Output
Capacitance
VOUT = 0V
7
9
pF
CI/O
I/O Port
Capacitance
VIN = 0V
7
9
pF
ALVC Link
NOTE:
NOTE:
NOTE:
NOTE:
NOTE:
1. These pins have โ€œBus-holdโ€. All other pins are standard inputs,
outputs, or I/Os.
Symbol
Description
Max.
Unit
VTERM(2)
Terminal Voltage
with Respect to GND
โ€“ 0.5 to + 4.6
V
VTERM(3)
Terminal Voltage
with Respect to GND
โ€“0.5 to
VCC + 0.5
V
TSTG
Storage Temperature
โ€“ 65 to + 150
ยฐC
IOUT
DC Output Current
โ€“ 50 to + 50
mA
IIK
Continuous Clamp Current,
VI < 0 or VI
> VCC
ยฑ 50
mA
IOK
Continuous Clamp Current, VO < 0
โ€“ 50
mA
ICC
ISS
Continuous Current through
each VCC or GND
ยฑ100
mA
ALVC Link
NOTE:
NOTE:
NOTE:
NOTE:
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Donโ€™t Care
Z = High-Impedance
โ†‘ = LOW-to-HIGH Transition
Q
0
= Level of Q before the indicated steady-state input conditions were
established.
Inputs
Output
OE
CLK
xD
xQ
L
โ†‘
HH
L
โ†‘
LL
LH or L
X
Q
0
HX
X
Z
Pin Names
Description
OE
3-State Output Enable Input (Active LOW)
CLK
Clock Input
xD
Data Inputs(1)
xQ
3-State Outputs
VCC
OE
8
D
7
D
7
Q
6
Q
6
D
5
D
5
Q
1
Q
1
D
2
D
2
Q
3
Q
3
D
4
D
4
Q
GND
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
SO20-2
SO20-7
SO20-8
SO20-9
CLK
8
Q


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