์ „์ž๋ถ€ํ’ˆ ๋ฐ์ดํ„ฐ์‹œํŠธ ๊ฒ€์ƒ‰์—”์ง„
  Korean  โ–ผ

Delete All
ON OFF
ALLDATASHEET.CO.KR

X  

Preview PDF Download HTML

74LVT16646 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 1 Page - Fairchild Semiconductor

๋ถ€ํ’ˆ๋ช… 74LVT16646
์ƒ์„ธ๋‚ด์šฉ  Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs
Download  9 Pages
Scroll/Zoom Zoom In 100% Zoom Out
์ œ์กฐ์‚ฌ  FAIRCHILD [Fairchild Semiconductor]
ํ™ˆํŽ˜์ด์ง€  http://www.fairchildsemi.com
Logo 

74LVT16646 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 1 Page - Fairchild Semiconductor

   
Zoom Inzoom in Zoom Outzoom out
/ 9 page
 1 / 9 page
background image
ยฉ 2001 Fairchild Semiconductor Corporation
DS012023
www.fairchildsemi.com
January 2000
Revised October 2001
74LVT16646 โ€ข 74LVTH16646
Low Voltage 16-Bit Transceiver/Register
with 3-STATE Outputs
General Description
The LVT16646 and LVTH16646 contains sixteen non-
inverting bidirectional registered bus transceivers providing
multiplexed transmission of data directly from the input bus
or from the internal storage registers. Each byte has sepa-
rate control inputs which can be shorted together for full
16-bit operation. The DIR inputs determine the direction of
data flow through the device. The CPAB and CPBA inputs
load data into the registers on the LOW-to-HIGH transition
(see Functional Description).
The LVTH16646 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These transceivers are designed for low-voltage (3.3V)
VCC applications, but with the capability to provide a TTL
interface to a 5V environment. The LVT16646 and
LVTH16646 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining low power dissipation.
Features
s Input and output interface capability to systems at
5V VCC
s Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH16646)
s Also available without bushold feature (74LVT16646)
s Live insertion/extraction permitted
s Power Up/Down high impedance provides
glitch-free bus loading
s Outputs source/sink
โˆ’32 mA/+64 mA
s Latch-up conforms to JEDEC JED78
s ESD performance:
Human-body model
> 2000V
Machine model
> 200V
Charged-device model
> 1000V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter โ€œXโ€ to the ordering code.
Logic Symbol
Order Number
Package Number
Package Description
74LVT16646MEA
(Preliminary)
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVT16646MTD
(Preliminary)
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LVTH16646MEA
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVTH16646MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide


Html Pages

1  2  3  4  5  6  7  8  9 


๋ฐ์ดํ„ฐ์‹œํŠธ Download




๋งํฌ URL



Privacy Policy
ALLDATASHEET.CO.KR
ALLDATASHEET ๊ฐ€ ๊ท€ํ•˜์— ๋„์›€์ด ๋˜์…จ๋‚˜์š”?  [ DONATE ]  

Alldatasheet๋Š”?   |   ๊ด‘๊ณ ๋ฌธ์˜    |   ์šด์˜์ž์—๊ฒŒ ์—ฐ๋ฝํ•˜๊ธฐ   |   ๊ฐœ์ธ์ •๋ณด์ทจ๊ธ‰๋ฐฉ์นจ   |   ์ฆ๊ฒจ์ฐพ๊ธฐ   |   ๋งํฌ๊ตํ™˜   |   ์ œ์กฐ์‚ฌ๋ณ„ ๊ฒ€์ƒ‰
All Rights Reservedยฉ Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn