AD

8339

Preliminary

Technical Data

Rev. PrA | Page 6 of 15

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

30

29

28

27

26

25

24

23

RF2N

RF2P

COMM

COMM

SCLK

CSB

VPOS

VPOS

Q2OP

I2OP

VPOS

VPOS

4LOP

4LON

VNEG

VNEG

Pin 1

Identifier

AD8339

Top View

(not to scale)

9

10

RF3P

RF3N

22

21

I3OP

Q3OP

Figure 2. 40-Lead LFCSP

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 2, 9, 10,

13, 14, 37,

38

RF1P-RF4P

RF1N-RF4N

RF Inputs. No internal bias. The optimum common mode voltage for maximum symmetrical input differential

swing is 2.5 V if

±5 V supplies are used.

3, 4, 15, 36

COMM

Ground

5

SCLK

Serial Interface – Clock

6

CSB

Serial Interface – Chip Select Bar. Active Low.

7, 8, 11,

16, 27, 28,

35

VPOS

Positive Supply. These pins should be decoupled with a ferrite bead in series with the supply, plus a 0.1

μF

and 1 nF capacitor between the VPOS pins and ground. Since the VPOS pins are internally connected, one set

of supply decoupling components on each side of the chip should be sufficient.

12

SDO

Serial Interface – Data Output. Normally connected to SDI of next chip or left open.

17

LODC

Decoupling Pin for LO. A 0.1

μF capacitor should be connected between this pin and ground. Value of cap

does influence chip enable/disable times.

18, 19, 21,

22, 29, 30,

32, 33

I1OP-I4OP,

Q1OP-Q4OP

I/Q Outputs. These outputs provide a bidirectional current that can be converted back to a voltage via a

transimpedance amplifier. Multiple outputs can be summed together through simply connecting them

(Wire-OR). The bias voltage should be set to 0 V or less by the transimpedance amplifier, see Figure 7.

20, 23, 24,

31

VNEG

Negative Supply. These pin should be decoupled with a ferrite bead in series with the supply, plus a 0.1

μF

and 1 nF capacitor between the pin and ground. Since the VNEG pins are internally connected, one set of

supply decoupling components should be sufficient.

25, 26

4LOP, 4LON

LO Inputs. No internal bias; optimally biased by an LVDS driver. For best performance, these inputs should be

driven differentially.

34

RSET

LO Interface - Reset. Logic threshold is at about 1.1 V and therefore can be driven by >1.8 V CMOS logic.

39

SDI

Serial Interface – Data Input. Logic threshold is at about 1.1 V and therefore can be driven by >1.8 V CMOS

logic.

40

RSTS

Reset for SPI Interface. Logic threshold is at about 1.1 V and therefore can be driven by >1.8 V CMOS logic. For

quick testing without the need to program the SPI, the voltage on the RSTS pin should be pulled to -1.4 V;

this enables all four channels in the Phase (I=1,Q=0) state.