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CS5112YDWF24G 데이터시트(PDF) 9 Page - ON Semiconductor

부품명 CS5112YDWF24G
상세설명  1.4 A Switching Regulator with 5.0 V, 100 mA Linear Regulator with Watchdog, RESET and ENABLE
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제조업체  ONSEMI [ON Semiconductor]
홈페이지  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

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9
APPLICATION NOTES
DESIGN PROCEDURE FOR BOOST TOPOLOGY
This section outlines a procedure for designing a boost
switching power supply operating in the discontinuous mode.
Step 1
Determine the output power required by the load.
POUT + IOUTVOUT
(1)
Step 2
Choose COSC based on the target oscillator frequency with
an external resistor value, RBIAS = 64.9 kW. (See Figure 5).
Step 3
Next select the output voltage feedback sense resistor
divider as follows (Figure 13).
For VFB1 active, choose a value for R1 and then solve for
REQ where:
REQ +
R1
VOUT
VFB1 *
1
(2)
For VFB2 active, find:
VFB1 + VOUT
REQ
R1 ) REQ
(3)
and then calculate R2 where:
R2 +
VR2
IR2
+
VFB1 * VFB2
VFB1 REQ
(4)
Then find R3, where:
R3 + REQ * R2
(5)
Figure 13. Feedback Sense Resistor Divider
Connected Between VOUT and Ground
VOUT
VFB1
VFB2
R1
R2
R3
VR2
REQ
Step 4
Determine the maximum on time at the minimum
oscillator frequency and VIN. For discontinuous operation,
all of the stored energy in the inductor is transferred to the
load prior to the next cycle. Since the current through the
inductor cannot change instantaneously and the inductance
is constant, a volt−second balance exists between the on time
and off time. The voltage across the inductor during the on
cycle is VIN and the voltage across the inductor during the
off cycle is VOUT − VIN.
Therefore:
VINtON + (VOUT * VIN)tOFF
(6)
where the maximum on time is:
tON(MAX) [ 1 *
VIN(MIN)
VOUT(MAX)
1
fSW(MIN)
(7)
Step 5
Calculate
the
maximum
inductance
allowed
for
discontinuous operation:
L(MAX) +
fSW(MIN)VIN2(MIN)tON2(MAX)
2POUT h
(8)
where
η = efficiency.
Usually
η = 0.75 is a good starting point. The IC’s power
dissipation should be calculated after the peak current has
been determined in Step 6. If the efficiency is less than
originally assumed, decrease the efficiency and recalculate
the maximum inductance and peak current.
Step 6
Determine the peak inductor current at the minimum
inductance, minimum VIN and maximum on time to make
sure the inductor current doesn’t exceed 1.4 A.
IPK +
VIN(MIN)tON(MAX)
L(MIN)
(9)
Step 7
Determine the minimum output capacitance and maximum
ESR based on the allowable output voltage ripple.
COUT(MIN) +
IPK
8f
DVRIPPLE
(10)
ESR(MIN) +
DVRIPPLE
IPK
(11)
In practice, it is normally necessary to use a larger
capacitance value to obtain a low ESR. By placing
capacitors in parallel, the equivalent ESR can be reduced.
Step 8
Compensate the feedback loop to guarantee stability
under all operating conditions. To do this, we calculate the
modulator gain and the feedback resistor network
attenuation and set the gain of the error amplifier so that the
overall loop gain is 0 dB at the crossover frequency, fCO. In
addition, the gain slope should be −20 dB/decade at the
crossover frequency.
The low frequency gain of the modulator (i.e. error
amplifier output to output voltage) is:
DVOUT
DVEA
+
IPK(MAX)
VEA(MAX)
RLOADLf
2
(12)
where:
IPK(MAX) +
VEA(MAX) GCSA
RS
+
2.4 V 7
150 m
W +
2.3 A (13)


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