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MC100EP29MNTXG 데이터시트(PDF) 2 Page - ON Semiconductor

부품명 MC100EP29MNTXG
상세설명  3.3V / 5V ECL Dual Differential Data and Clock D Flip?묯lop With Set and Reset
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제조업체  ONSEMI [ON Semiconductor]
홈페이지  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

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MC10EP29, MC100EP29
http://onsemi.com
2
VBB
Figure 1. 20−Lead Pinout (Top View) and Logic Diagram
CLK0
D1
CLK1
17
18
16
15
14
13
12
4
3
5678
9
Q0
11
10
Q0
S0
S1
VCC
Q1
Q1
VEE
D0
19
20
2
1
R0
VCC
CLK0
D1
D0
CLK1
R1
CLK
D
S
R
Q
Q
CLK
D
R
S
Q
Q
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
1
2
3
4
5
15
14
13
12
11
67
8
9
10
20
19
18
17
16
Figure 1. QFN−20 Pinout (Top View)
S0
Q0
Q0
D0
R0
VCC
Q1
Q1
R1
S1
VEE
CLK0
CLK0
CLK1
D0
VBB
CLK1
D1
D1
VCC
Exposed Pad
NOTE: The Exposed Pad (EP) on package bottom must be attached to a heat−sinking conduit.
The Exposed Pad may only be electrically connected to VEE.
MC10/100EP17
Table 1. PIN DESCRIPTION
Pin
Function
D0*, D0*; D1*, D1*
ECL Differential Data Inputs
R0*, R1*
ECL Reset Inputs
CLK0*, CLK0*
ECL Differential Clock Inputs
CLK1*, CLK1*
ECL Differential Clock Inputs
S0* S1*
ECL Set Inputs
Q0, Q0; Q1, Q1
ECL Differential Data Outputs
VBB
Reference Voltage Output
VCC
Positive Supply
VEE
Negative Supply
EP
Exposed Pad
*Pins will default LOW when left open.
Table 2. TRUTH TABLE
R
S
D
CLK
Q
Q
L
L
L
Z
L
H
L
L
H
Z
H
L
H
L
X
X
L
H
L
H
X
X
H
L
H
H
X
X
Undef
Undef
Z = LOW to HIGH Transition
X = Don’t Care


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