MC10H640, MC100H640

http://onsemi.com

2

1

VT

VT

Q1

GT GT

Q0

VT

GT

GT

Q4

Q5

VT

SEL

56

789

10

11

25

24

23

22

21

20

19

Q1

Figure 1. Pinout: PLCC−28

(Top View)

DE

DE

VE

R

GE

DT

Q0

VT

VT

Q3

GT

GT

Q2

4

3

2

28

27

26

18

17

16

15

14

13

12

Figure 2. Logic Diagram

TTL Outputs

TTL/ECL Clock Inputs

TTL Control Inputs

DE

DT

SEL

R

DE

MUX

÷ 2

÷ 4

Q0

Q1

Q2

Q3

Q0

Q1

Q4

Q5

Table 1. PIN DESCRIPTION

PIN

FUNCTION

GT

VT

VE

GE

DE, DE

DT

Qn, Qn

SEL

R

TTL Ground (0 V)

ECL Ground (0 V)

ECL Signal Input (positive ECL)

TTL Signal Input

Signal Outputs (TTL)

Input Select (TTL)

Reset (TTL)

Symbol

Characteristic

Condition

0°C

25°C

85°C

Min

Max

Min

Max

Min

Max

Unit

Power Supply Current

ECL

VE Pin

57

57

57

mA

TTL

Total all VT pins

30

30

30

mA

30

30

30

mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.