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MC100EP016AFA 데이터시트(PDF) 9 Page - ON Semiconductor |
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MC100EP016AFA 데이터시트(HTML) 9 Page - ON Semiconductor |
9 / 11 page MC100EP016A http://onsemi.com 9 Applications Information (continued) EP01 Q0 to Q7 P0 to P7 CLK TC PE CE Figure 6. 32-Bit Cascaded EP016A Programmable Divider LO CLK CLK CLK MSB LSB EP016 EP01 EP01 Q0 to Q7 Q0 to Q7 Q0 to Q7 Q0 to Q7 P0 to P7 P0 to P7 P0 to P7 EP016 EP016 EP016 CLK TC PE CE CLK CLK TC PE CE CLK CLK TC PE CE CLK Figure 6 shows a typical block diagram of a 32-bit divider chain. Once again to maximize the frequency of operation EP01 OR gates were used. For lower frequency applications a slower OR gate could replace the EP01. Note that for a 16-bit divider the OR function feeding the PE (program enable) input CANNOT be replaced by a wire OR tie as the TC output of the least significant EP016A must also feed the CE input of the most significant EP016A. If the two TC outputs were OR tied the cascaded count operation would not operate properly. Because in the cascaded form the PE feedback is external and requires external gating, the maximum frequency of operation will be significantly less than the same operation in a single device. Maximizing EP016A Count Frequency The EP016A device produces 9 fast transitioning single ended outputs, thus VCC noise can become significant in situations where all of the outputs switch simultaneously in the same direction. This VCC noise can negatively impact the maximum frequency of operation of the device. Since the device does not need to have the Q outputs terminated to count properly, it is recommended that if the outputs are not going to be used in the rest of the system they should be left unterminated. In addition, if only a subset of the Q outputs are used in the system only those outputs should be terminated. Not terminating the unused outputs will not only cut down the VCC noise generated but will also save in total system power dissipation. Following these guidelines will allow designers to either be more aggressive in their designs or provide them with an extra margin to the published data book specifications. Figure 7. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) Driver Device Receiver Device QD Q D Zo = 50 W Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V |
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