CAT24WC66

© 2006 Catalyst Semiconductor, Inc.

3

Doc. No. 1037 Rev. J

Characteristics subject to change without notice

AC CHARACTERISTICS

Memory Read & Write Cycle Limits

1.8V - 2.5V

4.5V - 5.5V

Units

Symbol

Parameter

Min

Max

Min

Max

FSCL

Clock Frequency

100

400

kHz

(1)

Noise Suppression Time Constant at

SCL, SDA Inputs

200

200

ns

SCL Low to SDA Data Out and ACK Out

3.5

1

µs

(1)

Time the Bus Must be Free Before a

New Transmission Can Start

4.7

1.2

µs

Start Condition Hold Time

4

0.6

µs

Clock Low Period

4.7

1.2

µs

Clock High Period

4

0.6

µs

Start Condition Setup Time

(for a Repeated Start Condition)

4.7

0.6

µs

Data In Hold Time

0

0

ns

Data In Setup Time

50

50

ns

(1)

SDA and SCL Rise Time

1

0.3

µs

(1)

SDA and SCL Fall Time

300

300

ns

Stop Condition Setup Time

4

0.6

µs

Data Out Hold Time

100

100

ns

Power-Up Timing

(1) (2)

Symbol

Parameter

Min

Typ

Max

Units

Power-Up to Read Operation

1

ms

Power-Up to Write Operation

1

ms

Notes:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

Write Cycle Limits

Symbol

Parameter

Min

Typ

Max

Units

Write Cycle Time

10

ms

The write cycle time is the time from a valid stop

condition of a write sequence to the end of the internal

program/erase cycle. During the write cycle, the bus

interface circuits are disabled, SDA is allowed to

remain high, and the device does not respond to its

slave address.