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MC10162FN 데이터시트(PDF) 1 Page - ON Semiconductor

부품명 MC10162FN
상세설명  Binary to 1-8 Decoder (High)
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제조업체  ONSEMI [ON Semiconductor]
홈페이지  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC10162FN 데이터시트(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2002
January, 2002 – Rev. 7
1
Publication Order Number:
MC10162/D
MC10162
Binary to 1-8 Decoder
(High)
The MC10162 is designed to convert three lines of input data to a
one–of–eight output. The selected output will be high while all other
outputs are low. The enable inputs, when either or both are high, force
all outputs low.
The MC10162 is a true parallel decoder. No series gating is used
internally, eliminating unequal delay times found in other decoders.
This device is ideally suited for demultiplexer applications. One of
the two enable inputs is used as the data input, while the other is used
as a data enable input.
A complete mux/demux operation on 16 bits for data distribution is
illustrated in Figure 1 of the MC10161 data sheet.
P
D = 315 ns typ/pkg (No Load)
t
pd = 4.0 ns typ
t
r, tf = 2.0 ns typ (20%–80%)
LOGIC DIAGRAM
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
E02
E115
A7
B9
C14
6Q0
5Q1
4Q2
3Q3
13Q4
12Q5
11Q6
10Q7
TRUTH TABLE
INPUTS
OUTPUTS
E0
E1
C
B
A
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
L
L
H
L
L
L
H
L
L
L
L
L
L
L
L
H
H
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
H
L
H
L
L
L
L
L
H
L
L
L
L
H
H
L
L
L
L
L
L
L
H
L
L
L
H
H
H
L
L
L
L
L
L
L
H
H
X
X
X
X
L
L
L
L
L
L
L
L
X
H
X
X
X
L
L
L
L
L
L
L
L
http://onsemi.com
Device
Package
Shipping
ORDERING INFORMATION
MC10162L
CDIP–16
25 Units / Rail
MC10162P
PDIP–16
25 Units / Rail
MC10162FN
PLCC–20
46 Units / Rail
MARKING
DIAGRAMS
1
16
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
CDIP–16
L SUFFIX
CASE 620
MC10162L
AWLYYWW
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
10162
AWLYYWW
1
1
16
MC10162P
AWLYYWW
DIP PIN ASSIGNMENT
VCC1
E0
Q3
Q2
Q1
Q0
A
VEE
VCC2
E1
C
Q4
Q5
Q6
Q7
B
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables
on page 18 of the ON Semiconductor MECL Data Book
(DL122/D).


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