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MC10175P 데이터시트(PDF) 1 Page - ON Semiconductor

부품명 MC10175P
상세설명  Quint Latch
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제조업체  ONSEMI [ON Semiconductor]
홈페이지  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2002
January, 2002 – Rev. 7
1
Publication Order Number:
MC10175/D
MC10175
Quint Latch
The MC10175 is a high speed, low power quint latch. It features five
D type latches with common reset and a common two–input clock.
Data is transferred on the negative edge of the clock and latched on the
positive edge. The two clock inputs are “OR”ed together.
Any change on the data input will be reflected at the outputs while
the clock is low. The outputs are latched on the positive transition of
the clock. While the clock is in the high state, a change in the
information present at the data inputs will not affect the output
information. The reset input is enabled only when the clock is in the
high state.
P
D = 400 mW typ/pkg (No Load)
t
pd = 2.5 ns typ (Data to Output)
t
r, tf = 2.0 ns typ (20%–80%)
LOGIC DIAGRAM
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
10
14
D
C
Q
R
6
7
11
D
C
Q
R
D
C
Q
R
D
C
Q
R
D
C
Q
R
15
3
4
12
9
5
13
D0
C0
C1
RESET
D1
D3
D4
D2
2
Q0
Q1
Q3
Q4
Q2
TRUTH TABLE
D
C0
C1
Reset
Qn+1
L
L
L
X
L
H
L
L
X
H
X
H
X
L
Q n
X
X
H
L
Q n
X
H
X
H
L
X
X
H
H
L
http://onsemi.com
Device
Package
Shipping
ORDERING INFORMATION
MC10175L
CDIP–16
25 Units / Rail
MC10175P
PDIP–16
25 Units / Rail
MC10175FN
PLCC–20
46 Units / Rail
MARKING
DIAGRAMS
1
16
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
CDIP–16
L SUFFIX
CASE 620
MC10175L
AWLYYWW
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775
10175
AWLYYWW
1
1
16
MC10175P
AWLYYWW
DIP PIN ASSIGNMENT
VCC1
Q2
Q3
Q4
D4
C0
C1
VEE
VCC2
Q1
Q0
D2
D1
RESET
D0
D3
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables
on page 18 of the ON Semiconductor MECL Data Book
(DL122/D).


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