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NBSG16M 데이터시트(PDF) 3 Page - ON Semiconductor |
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NBSG16M 데이터시트(HTML) 3 Page - ON Semiconductor |
3 / 11 page NBSG16M http://onsemi.com 3 50 W 50 W VTD D D VTD Q Q VBB VEE VCC 50 W 50 W Figure 2. Logic Diagram Q Q VCC 16 mA 50 W 50 W Figure 3. CML Output Structure VEE Table 2. Interfacing Options INTERFACING OPTIONS CONNECTIONS CML Connect VTD and VTD to VCC LVDS Connect VTD and VTD together AC−COUPLED Bias VTD and VTD Inputs within (VIHCMR) Common Mode Range RSECL, PECL, NECL Standard ECL Termination Techniques LVTTL, LVCMOS An external voltage should be applied to the unused complementary differential input. Nominal voltage 1.5 V for LVTTL and VCC/2 for LVCMOS inputs. Table 3. ATTRIBUTES Characteristics Value ESD Protection Human Body Model Machine Model Charged Device Model > 1 kV > 100 V > 4 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 4) Pb Pkg Pb−Free Pkg QFN−16 Level 1 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 145 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 4. For additional Moisture Sensitivity information, refer to Application Note AND8003/D. |
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