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AD8612ARUZ 데이터시트(PDF) 6 Page - Analog Devices |
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AD8612ARUZ 데이터시트(HTML) 6 Page - Analog Devices |
6 / 20 page AD8611/AD8612 Rev. A | Page 6 of 20 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS V+ IN+ V– IN– QA QA GND LATCH 1 2 3 4 8 7 6 5 AD8611 TOP VIEW (Not to Scale) QA V+ 1 IN+ 2 IN– 3 V– 4 8 QA 7 GND 6 LATCH 5 AD8611 TOP VIEW (Not to Scale) GND LEA V– INA– INA+ GND LEB V+ INB– INB+ QA QA QB QB 1 2 3 4 5 6 7 AD8612 14 13 12 11 10 9 8 TOP VIEW (Not to Scale) Figure 4. 8-Lead Narrow Body SOIC Pin Configuration Figure 5. 8-Lead MSOP Pin Configuration Figure 6. 14-Lead TSSOP Pin Configuration Table 5. Pin Function Descriptions Pin No. SOIC and MSOP TSSOP Mnemonic Description 1 10 V+ Positive Supply Terminal. 2 IN+ Noninverting Analog Input of the Differential Input Stage. 3 IN− Inverting Analog Input of the Differential Input Stage. 4 5 V− Negative Supply Terminal. 5 LATCH Latch Enable Input. 6 3, 12 GND Negative Logic Supply 7 1 QA One of Two Complementary Output for Channel A. 8 2 QA One of Two Complementary Output for Channel A. 14 QB One of Two Complementary Output for Channel B. 13 QB One of Two Complementary Output for Channel B. 4 LEA Channel A Latch Enable. 11 LEB Channel B Latch Enable. 7 INA+ Noninverting Analog Input of the Differential Input Stage for Channel A. 6 INA− Inverting Analog Input of the Differential Input Stage for Channel A. 8 INB+ Noninverting Analog Input of the Differential Input Stage for Channel B. 9 INB− Inverting Analog Input of the Differential Input Stage for Channel B. |
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