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CDP68HC68A2 데이터시트(PDF) 3 Page - Intersil Corporation

부품명 CDP68HC68A2
상세설명  CMOS Serial 10-Bit A/D Converter
Download  15 Pages
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제조업체  INTERSIL [Intersil Corporation]
홈페이지  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CDP68HC68A2 데이터시트(HTML) 3 Page - Intersil Corporation

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3
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . . . -0.5V to +7V
(Voltage Referenced to VSS Terminal)
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input
. . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Conditions (Note 1)
Temperature Ambient, TA . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
DC Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . 3V Min, 6V Max
Thermal Resistance (Typical, Note 2)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
Maximum Power Dissipation Per Package (PD)
TA = -40oC to 60oC (Package Type E) . . . . . . . . . . . . . . .500mW
TA = 60oC to 85oC (Package Type E)
Derate Linearly at. . . . . . . . . . . . . . . . . . . 12mW/oC to 200mW
TA = -40oC to 70oC (Package Type M) (Note 3) . . . . . . . .400mW
TA = -70oC to 85oC (Package Type M) (Note 3)
Derate Linearly at. . . . . . . . . . . . . . . . . . . 6.0mW/oC to 310mW
Device Dissipation Per Output Transistor . . . . . . . . . . . . . . . .40mW
TA = Full Package Temperate Range (All Package Types)
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range (TSTG) . . . . . -65oC to 150oC
Maximum Lead Temperature (During Soldering). . . . . . . . . . .265oC
At Distance 1/16
±1/32 In. (1.59 ± 0.79mm)
From Case for 10s Max (SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. For maximum reliability, nominal operating conditions should be selected so that operation is always within the ranges specified.
2.
θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
3. Printed circuit board mount: 58mm x 57mm minimum area x 1.6mm thick G10 epoxy glass, or equivalent.
Electrical Specifications TA = 25oC, VDD = 5V, Unless Otherwise Specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ACCURACY
Differential Linearity Error
10-Bit Mode
-
±1.25
±2LSB
Integral Linear Error
10-Bit Mode
-
±1.25
±2LSB
Offset Error
10-Bit Mode
-1
3
4
LSB
Gain Error
10-Bit Mode
-1
1
2
LSB
ANALOG INPUTS: AI0 THRU AI7
Input Resistance
In Series with Sample Caps
-
85
-
Sample Capacitance
During Sample State
-
400
-
pF
Input Capacitance
During Hold State
-
20
-
pF
Input Current
At VIN = VREF + During Sample
During Hold or Standby State
-+30
-
µA
--
±1
µA
Input + Full Scale Range
From Input RC Time Constant
VR = 1
VSS
-VDD
+0.3
V
Input Bandwidth (3dB)
-4.68
-
MHz
Input Voltage Range: AI0
3.0
-
VDD
V
DIGITAL INPUTS: MOSI, SCK, CE, TA = -40oC to 85oC
High Input Voltage
VIH
VDD = 3 to 6V
70
-
-
% of
VDD
Low Input Voltage
VIL
VDD = 3 to 6V
-
-
30
% of
VDD
Input Leakage
--
±1
µA
Input Capacitance
TA = 25oC-
-
10
pF
CDP68HC68A2


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