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MM74HC595 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 5 Page - Fairchild Semiconductor

๋ถ€ํ’ˆ๋ช… MM74HC595
์ƒ์„ธ๋‚ด์šฉ  8-Bit Shift Registers with Output Latches
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MM74HC595 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 5 Page - Fairchild Semiconductor

 
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AC Electrical Characteristics (Continued)
Note 6: CPD determines the no load dynamic power consumption, PD = CPD VCC
2f
+ I
CC VCC, and the no load dynamic current consumption,
IS = CPD VCC f + ICC.
Symbol
Parameter
Conditions
VCC
TA = 25ยฐCTA = โˆ’40 to 85ยฐCTA = โˆ’55 to 125ยฐC
Units
Typ
Guaranteed Limits
tPHZ, tPLZ Maximum Output Disable
RL = 1 kโ„ฆ
2.0V
75
175
220
265
ns
Time from G to QA thru QH
CL = 50 pF
4.5V
15
35
44
53
6.0V
13
30
37
45
tS
Minimum Setup Time
2.0V
100
125
150
ns
from SER to SCK
4.5V
20
25
30
6.0V
17
21
25
tR
Minimum Removal Time
2.0V
50
63
75
ns
from SCLR to SCK
4.5V
10
13
15
6.0V
9
11
13
tS
Minimum Setup Time
2.0V
100
125
150
ns
from SCK to RCK
4.5V
20
25
30
6.0V
17
21
26
tH
Minimum Hold Time
2.0V
5
5
5
ns
SER to SCK
4.5V
5
5
5
6.0V
5
5
5
tW
Minimum Pulse Width
2.0V
30
80
100
120
ns
of SCK or SCLR
4.5V
9
16
20
24
6.0V
8
14
18
22
tr, tf
Maximum Input Rise and
2.0V
1000
1000
1000
ns
Fall Time, Clock
4.5V
500
500
500
6.0V
400
400
400
tTHL, tTLH Maximum Output
2.0V
25
60
75
90
ns
Rise and Fall Time
4.5V
7
12
15
18
QAโ€“QH
6.0V
6
10
13
15
tTHL, tTLH Maximum Output
2.0V
75
95
110
ns
Rise & Fall Time
4.5V
15
19
22
Q'H
6.0V
13
16
19
CPD
Power Dissipation
G
= V
CC
90
pF
Capacitance, Outputs
G
= GND
150
Enabled (Note 6)
CIN
Maximum Input
5
10
10
10
pF
Capacitance
COUT
Maximum Output
15
20
20
20
pF
Capacitance


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