전자부품 데이터시트 검색엔진 |
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CA3310AM 데이터시트(PDF) 6 Page - Intersil Corporation |
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CA3310AM 데이터시트(HTML) 6 Page - Intersil Corporation |
6 / 16 page 6 Timing Diagrams FIGURE 1. FREE RUNNING, STRT TIED LOW, DRST TIED HIGH FIGURE 2. OUTPUT ENABLE/DISABLE TIMING DIAGRAM FIGURE 3. STRT PULSED LOW, DRST TIED HIGH, INTERNAL CLOCK 12 3 4 5 - 12 13 1 23 tD1 DRDY CLK DRDY D0 - D9 INPUT tD DATA DATA N - 1 TRACK N HOLD tD APR DATA N TRACK N + 1 tLOW tHIGH tD2 DRDY OEL OR OEM D0 - D1 OR tDIS tEN 50% 50% 10% 90% OFF TO LOW TO OUTPUT PIN OFF TO HIGH D2- D9 ZL = 50pF TO GND 1k Ω TO VDD ZL = 50pF TO GND 1k Ω TO GND CLK (INTERNAL) 13 1 2 345 tR STRT STRT DRDY INPUT HOLD TRACK HOLD tD3 DRDY tW STRT tD CLK DON’T CARE CA3310, CA3310A |
유사한 부품 번호 - CA3310AM |
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유사한 설명 - CA3310AM |
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