전자부품 데이터시트 검색엔진 |
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AD7520 데이터시트(PDF) 4 Page - Intersil Corporation |
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AD7520 데이터시트(HTML) 4 Page - Intersil Corporation |
4 / 10 page 4 Definition of Terms Nonlinearity: Error contributed by deviation of the DAC transfer function from a “best straight line” through the actual plot of transfer function. Normally expressed as a percentage of full scale range or in (sub)multiples of 1 LSB. Resolution: It is addressing the smallest distinct analog output change that a D/A converter can produce. It is commonly expressed as the number of converter bits. A converter with resolution of N bits can resolve output changes of 2-N of the full-scale range, e.g., 2-N VREF for a unipolar conversion. Resolution by no means implies linearity. Settling Time: Time required for the output of a DAC to settle to within specified error band around its final value (e.g., 1/2 LSB) for a given digital input change, i.e., all digital inputs LOW to HIGH and HIGH to LOW. Gain Error: The difference between actual and ideal analog output values at full scale range, i.e., all digital inputs at HIGH state. It is expressed as a percentage of full scale range or in (sub)multiples of 1 LSB. Feedthrough Error: Error caused by capacitive coupling from VREF to IOUT1 with all digital inputs LOW. Output Capacitance: Capacitance from IOUT1 and IOUT2 terminals to ground. Output Leakage Current: Current which appears on IOUT1 terminal when all digital inputs are LOW or on IOUT2 terminal when all digital inputs are HIGH. Detailed Description The AD7520 and AD7521 are monolithic, multiplying D/A converters. A highly stable thin film R-2R resistor ladder network and NMOS SPDT switches form the basis of the converter circuit, CMOS level shifters permit low power TTL/CMOS compatible operation. An external voltage or current reference and an operational amplifier are all that is required for most voltage output applications. A simplified equivalent circuit of the DAC is shown in the Functional Diagram. The NMOS SPDT switches steer the ladder leg currents between IOUT1 and IOUT2 buses which must be held either at ground potential. This configuration maintains a constant current in each ladder leg independent of the input code. Converter errors are further reduced by using separate metal interconnections between the major bits and the outputs. Use of high threshold switches reduce offset (leakage) errors to a negligible level. The level shifter circuits are comprised of three inverters with positive feedback from the output of the second to the first, see Figure 1. This configuration results in TTL/CMOS compatible operation over the full military temperature range. With the ladder SPDT switches driven by the level shifter, each switch is binarily weighted for an ON resistance proportional to the respective ladder leg current. This assures a constant voltage drop across each switch, creating equipotential terminations for the 2R ladder resistors and highly accurate leg currents. V+ DTL/TTL/ CMOS INPUT 13 4 5 6 7 2 89 TO LADDER IOUT2 IOUT1 FIGURE 1. CMOS LEVEL SHIFTER AND SWITCH Test Circuits The following test circuits apply for the AD7520. Similar circuits are used for the AD7521. FIGURE 2. NONLINEARITY FIGURE 3. POWER SUPPLY REJECTION 10-BIT BINARY COUNTER GND 15 16 1 5 4 13 32 AD7520 BIT 1 (MSB) BIT 10 (LSB) LINEARITY ERROR x 100 RFEEDBACK IOUT1 IOUT2 HA2600 - + VREF BIT 1 (MSB) BIT 10 BIT 11 BIT 12 10k Ω 0.01% 1M Ω 10k Ω 0.01% CLOCK +15V VREF HA2600 - + 12-BIT REFERENCE DAC 15 16 1 5 4 13 32 AD7520 BIT 1 (MSB) BIT 10 (LSB) HA2600 - + HA2600 - + 500k Ω UNGROUNDED SINE WAVE GENERATOR 40Hz 1VP-P 5k Ω 0.01% 5K 0.01% RFEEDBACK +15V +10V VREF IOUT1 IOUT2 14 GND VERROR x 100 AD7520, AD7521 |
유사한 부품 번호 - AD7520_02 |
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유사한 설명 - AD7520_02 |
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