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CA3318CD 데이터시트(PDF) 7 Page - Intersil Corporation

부품명 CA3318CD
상세설명  CMOS Video Speed, 8-Bit, Flash A/D Converter
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제조업체  INTERSIL [Intersil Corporation]
홈페이지  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CA3318CD 데이터시트(HTML) 7 Page - Intersil Corporation

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7
Theory of Operation
A sequential parallel technique is used by the CA3318
converter to obtain its high speed operation. The sequence
consists of the “Auto-Balance” phase,
φ1, and the “Sample
Unknown” phase,
φ2. (Refer to the circuit diagram.) Each
conversion takes one clock cycle (see Note). With the phase
control (pin 19) high, the “Auto-Balance” (
φ1) occurs during
the high period of the clock cycle, and the “Sample Unknown”
(
φ2) occurs during the low period of the clock cycle.
NOTE: The device requires only a single phase clock The terminology
of
φ1 and φ2 refers to the high and low periods of the same clock.
During the “Auto-Balance” phase, a transmission switch is
used to connect each of the first set of 256 commutating
capacitors to their associated ladder reference tap. Those
tap voltages will be as follows:
VTAP (N) = [(N/256) VREF] - (1/512) VREF]
= [(2N - 1)/512] VREF,
Where:
VTAP (n) = reference ladder tap voltage at point n,
VREF
= voltage across VREF- to VREF+,
N
= tap number (1 through 256).
The other side of these capacitors are connected to single-
stage amplifiers whose outputs are shorted to their inputs by
switches. This balances the amplifiers at their intrinsic trip
points, which is approximately (VAA+ - VAA-)/2. The first set
of capacitors now charges to their associated tap voltages.
FIGURE 10. ENOB vs INPUT FREQUENCY
Typical Performance Curves (Continued)
fI (MHz)
8.0
5.0
7.6
7.2
6.8
6.4
6.0
5.6
5.2
4.8
4.4
4.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
fS = 15MHz
Pin Descriptions
PIN
NAME
DESCRIPTION
1
B1
Bit 1 (LSB)
Output Data Bits
(High = True)
2B2
Bit 2
3B3
Bit 3
4B4
Bit 4
5B5
Bit 5
6B6
Bit 6
7B7
Bit 7
8
B8
Bit 8 (MSB)
9
OF
Overflow
10
1/
4 R
Reference Ladder 1/4 Point
11
VSS
Digital Ground
12
VDD
Digital Power Supply, +5V
13
CE2
Three-State Output Enable Input,
Active Low, See Truth Table.
14
CE1
Three-State Output Enable Input
Active High. See Truth Table.
15
VREF-
Reference Voltage Negative Input
16
VIN
Analog Signal Input
17
VAA-
Analog Ground
18
CLK
Clock Input
19
PHASE
Sample clock phase control input.
When PHASE is low, “Sample
Unknown” occurs when the clock is
low and “Auto Balance” occurs when
the clock is high (see text).
20
1/
2 R
Reference Ladder Midpoint
21
VIN
Analog Signal Input
22
VREF+
Reference Voltage Positive Input
23
3/
4 R
Reference Ladder 3/4 Point
24
VAA+
Analog Power Supply, +5V
CHIP ENABLE TRUTH TABLE
CE1
CE2
B1 - B8
OF
0
1
Valid
Valid
1
1
Three-State
Valid
X
0
Three-State
Three-State
X = Don’t Care
CA3318


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