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AM29DL322D ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 4 Page - Advanced Micro Devices

๋ถ€ํ’ˆ๋ช… AM29DL322D
์ƒ์„ธ๋‚ด์šฉ  32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
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์ œ์กฐ์‚ฌ  AMD [Advanced Micro Devices]
ํ™ˆํŽ˜์ด์ง€  http://www.amd.com
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AM29DL322D ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 4 Page - Advanced Micro Devices

 
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December 13, 2005
Am29DL322D/323D/324D
3
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 7
Special Handling Instructions for FBGA Package .......................... 8
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10
Word/Byte Configuration .............................................................. 10
Requirements for Reading Array Data ......................................... 10
Writing Commands/Command Sequences .................................. 11
Simultaneous Read/Write Operations
with Zero Latency ......................................................................... 11
Standby Mode .............................................................................. 11
Automatic Sleep Mode ................................................................. 11
RESET#: Hardware Reset Pin ..................................................... 12
Output Disable Mode ................................................................... 12
Autoselect Mode .......................................................................... 17
Sector/Sector Block Protection and Unprotection ........................ 18
Write Protect (WP#) ..................................................................... 19
Temporary Sector Unprotect ........................................................ 19
Figure 1. Temporary Sector Unprotect Operation................................. 19
Figure 2. In-System Sector Protection/
Sector Unprotection Algorithms ............................................................ 20
SecSi
TM (Secured Silicon) Sector
Flash Memory Region .................................................................. 21
Hardware Data Protection ............................................................ 22
Common Flash Memory Interface (CFI) . . . . . . . 22
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 25
Reading Array Data ...................................................................... 25
Reset Command .......................................................................... 26
Autoselect Command Sequence .................................................. 26
Enter SecSiTM Sector/Exit SecSi Sector
Command Sequence ................................................................... 26
Byte/Word Program Command Sequence ................................... 26
Figure 3. Program Operation ................................................................ 27
Chip Erase Command Sequence ................................................. 27
Sector Erase Command Sequence .............................................. 28
Erase Suspend/Erase Resume Commands ................................ 28
Figure 4. Erase Operation..................................................................... 29
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 31
DQ7: Data# Polling ...................................................................... 31
Figure 5. Data# Polling Algorithm ......................................................... 31
RY/BY#: Ready/Busy# ................................................................. 32
DQ6: Toggle Bit I .......................................................................... 32
Figure 6. Toggle Bit Algorithm .............................................................. 32
DQ2: Toggle Bit II ......................................................................... 33
Reading Toggle Bits DQ6/DQ2 .................................................... 33
DQ5: Exceeded Timing Limits ...................................................... 33
DQ3: Sector Erase Timer ............................................................. 33
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 35
Figure 7. Maximum Negative Overshoot Waveform............................. 35
Figure 8. Maximum Positive Overshoot Waveform .............................. 35
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 9. I
CC1 Current vs. Time (Showing Active and
Automatic Sleep Currents).................................................................... 37
Figure 10. Typical I
CC1 vs. Frequency................................................... 37
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 11. Test Setup .......................................................................... 38
Figure 12. Input Waveforms and Measurement Levels ........................ 38
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 13. Read Operation Timings...................................................... 39
Figure 14. Reset Timings...................................................................... 40
Word/Byte Configuration (BYTE#) ............................................... 41
Figure 15. BYTE# Timings for Read Operations .................................. 41
Figure 16. BYTE# Timings for Write Operations .................................. 41
Erase and Program Operations ................................................... 42
Figure 17. Program Operation Timings ................................................ 43
Figure 18. Accelerated Program Timing Diagram ................................ 43
Figure 19. Chip/Sector Erase Operation Timings ................................. 44
Figure 20. Back-to-back Read/Write Cycle Timings ............................. 45
Figure 21. Data# Polling Timings (During Embedded Algorithms) ....... 45
Figure 22. Toggle Bit Timings (During Embedded Algorithms) ............ 46
Figure 23. DQ2 vs. DQ6 ....................................................................... 46
Temporary Sector Unprotect ........................................................ 47
Figure 24. Temporary Sector Unprotect Timing Diagram..................... 47
Figure 25. Sector/Sector Block Protect and Unprotect Timing Diagram 48
Alternate CE# Controlled Erase and Program Operations ........... 49
Figure 26. Alternate CE# Controlled Write (Erase/Program)
Operation Timings ................................................................................ 50
Erase And Programming Performance . . . . . . . 51
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 51
TSOP And SO Pin Capacitance . . . . . . . . . . . . . . 51
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 52
FBD063โ€”63-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 14 mm . 52
TS 048โ€”48-Pin Standard TSOP ................................................. 53
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 54


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